Physical Design Engineer, Staff - Hod Hasharon

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General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

About the Role

• As a Senior Physical Design Engineer, you will take ownership of block-level and subsystem-level physical implementation, driving timing closure and physical sign-off on advanced process nodes. You will also contribute to flow development and begin integrating Agentic AI methodologies into the team's design automation practices.TSMC N5 / N4P / N3Python • TCLAgentic AIFlow DevelopmentMulti-Patterning

What You'll Do

• Lead floorplanning, placement, CTS, routing, and optimization for high-speed digital blocks and subsystemsDrive timing closure including clock skew balancing, OCV handling, MCMM analysis, and ECO implementationConduct and own signal integrity, power integrity, IR drop, and electromigration analysis (RedHawk / Voltus)Run full signoff verification flows (DRC, LVS, DFM, EM/IR,)Develop and maintain backend PD flows using Python and TCL-based automation for PnR, STA, and physical verificationDrive Agentic AI integration - leverage AI-assisted tools for automated constraint optimization, timing ECO suggestions, and intelligent violation triageOptimize power and area via Multi-Vt optimization, clock gating, and power-aware synthesisCollaborate cross-functionally with front-end, DFT, verification, and process teams to resolve design and manufacturing issues

What You'll Need

• 3-8 years of experience in digital Physical Design (Backend) methodologies
• Experience with advanced process nodes (TSMC N5, N4P, N3, or equivalent FinFET)Proficiency in EDA tools: Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk / VoltusStrong understanding of floorplanning, CTS, PnR, STA, IR drop/EM analysis, and power optimizationSolid scripting skills in Python and TCL - ability to build and maintain design automation flowsHands-on flow development experience: building reusable scripts, run environments, and regression frameworksExposure to or curiosity about Agentic AI-driven EDA methodologiesFamiliarity with DFT concepts (scan insertion, ATPG, BIST) is a plus

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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