Pre/Post Silicon Validation Engineer with PMIC Expertise

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General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Our team is part of the SoC Silicon Validation Engineering group and is at the forefront of Silicon level HW architectural validation, tasked with uncovering design implementation bugs through rigorous pre/post-silicon system level validation. We are seeking a dynamic individual with 4-8 years of experience to validate Power Management Integrated Circuits (PMICs) from the SoC perspective. The ideal candidate will have a strong understanding of PMIC internals, the SoC-PMIC control interface (SPMI or similar controllers and protocols), and the sleep/wake and power sequencing flows between the SoC and PMIC. They will be instrumental in defining and executing SoC level use cases and scenarios, debugging complex power issues on silicon using lab tools, and ensuring seamless functionality, robustness and performance of the SoC power delivery and power management infrastructure.

Responsibilities:

• Develop and execute validation plans and coverage, leveraging expertise in PMICs to enhance system-level validation strategies.
• SoC-PMIC interface validation: Validate the SPMI (or similar, e.g., I2C/I3C) controller, PMIC arbiter and protocol behavior, including command sequences, arbitration across multiple masters, register access, interrupt handling and error/fault scenarios.
• Sleep/wake and power sequencing: Define and execute scenarios covering power-on/power-off, reset, sleep entry/exit and wake-up sequences, including rail ramp/retention/collapse, clock (XO) handling, PMIC mode transitions and wake sources such as interrupts, RTC alarms and key presses.
• Rail and regulator validation: Validate SoC-driven voltage scaling (DVFS/AVS), regulator mode switching (e.g., PWM/PFM, low-power/high-power), slew rates, settling times and voltage margins across supply rails.
• Collaborate closely with cross-functional teams (SoC design, PMIC design/systems, power architecture, firmware and software) to validate power management subsystems and SoC Power infrastructure.
• Measure and analyze power/performance characteristics of SoCs, with a focus on PMIC integration, rail-level current, sleep floor current and transition behavior.
• Create random stress stimulus validation frameworks, incorporating PMIC scenarios (concurrent rail transitions, repeated sleep/wake cycles, load transients, interface traffic) to test system resilience and reliability.
• Debug and root-cause silicon failures using lab tools, waveform captures and protocol traces; clearly document issues and drive them to closure with design and firmware teams.
• Contribute to pre-silicon validation (emulation/FPGA platforms) to ensure PMIC-related scenarios are ready ahead of silicon arrival.

Job Qualifications:

• Bachelor's/Master's in Electrical/Electronic Engineering or Computer Engineering.
• 4-8 years of relevant industry experience in PMICs, defining and executing SOC level use cases and scenarios.
• PMIC internals: Strong understanding of buck/SMPS regulators, LDOs, operating modes, power-on/power-off logic, PMIC GPIOs, ADCs, RTC, temperature alarms and protection mechanisms (OCP, OVP, UVLO).
• Interface and protocol: Hands-on experience with SPMI or similar controllers and protocols (I2C/I3C), including PMIC arbitration, register access and interrupt flows.
• Sleep/wake sequences: Good understanding of SoC-PMIC power sequencing, system sleep/wake flows, rail retention/collapse, and the role of power management controllers/firmware in these transitions.
• Proven experience interfacing with Power Management IC, DVFS, and system low power modes.
• Proficiency in C & Python programming for content development and scripting.
• Familiarity with ARM SoC concepts and architecture specifications like SMMU, GIC, Coresight.
• Lab tools: Strong debugging skills, with hands-on experience using Lab Equipment such as Oscilloscopes, Logic Analyzers, Protocol Analyzers (SPMI/I2C), Power Analyzers/Source Measure Units, DMMs, Electronic Loads, Current Probes and Lauterbach debuggers.
• Excellent communication, interpersonal, and problem-solving skills, with the ability to quickly adapt to new environments and technologies.

Preferred Qualifications:

• Experience with multi-PMIC platforms, PMIC-related firmware (boot, power management controller firmware) and Linux/RTOS power management drivers.
• Exposure to board-level power delivery, schematics review and power-integrity concepts (load transients, droop, ripple).
• Knowledge of thermal and limits management (temperature sensing, current limiting, throttling) and battery/charger subsystems.
• Experience with lab automation and data analysis using Python for instrument control and large-scale regression.
• Exposure to pre-silicon validation on emulation/FPGA platforms.

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