Principal PCIe CXL RTL Design Engineer

This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe and CXL standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.

Rambus offers a flexible work environment, embracing a hybrid approach. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Benefits include an excellent health insurance, Employee Stock Purchase Plan, an extra day of vacation per quarter, regular team lunches and breakfasts and a great team atmosphere.