Senior Quantum Engineer, Gate Calibration

We are looking for an experienced Quantum Engineer to drive the two-qubit gate performance of our tunable-coupler superconducting quantum processors.

Two-qubit gate fidelity is one of the most consequential challenges in quantum computing, and it sits at the center of our roadmap toward error correction. In this role, you will design, execute, and interpret the experiments that propel our near- and long-term gate performance at scale. You will identify the dominant sources of two-qubit gate error on our processors, isolate their physical origin, and eliminate them - through pulse engineering, calibration methodology, error suppression strategies, or feedback to design and fabrication. Your conclusions will directly inform device design, control strategy, and platform-level decisions.

This is a role with substantial autonomy and ownership. You will directly influence the technical direction for gate performance work through the rigorous design and execution of your test plans, measurement and improvement of relevant metrics and error budgeting, and shaping of research priorities. You will do this in a deeply collaborative environment spanning device design, fabrication, control systems, software, theory and R&D, turning proofs of concept into robust procedures that hold up across hundreds of qubit pairs.

Key Responsibilities

• Lead experimental programs to characterize, calibrate, and optimize two-qubit gates on tunable-coupler devices, from single-pair physics investigations to full-processor deployment.

• Identify gate-error bottlenecks (e.g., coherent control error, decoherence, leakage, crosstalk, TLS interactions) for single-pair as well as large-scale systems and isolate their physical origin through targeted experiments, benchmarking, and simulation.

• Develop and harden calibration methods using techniques such as optimal pulse shaping, dynamical decoupling, and other error suppression strategies, with an emphasis on robustness and automation at scale.

• Develop and improve metrology for full-processor Hamiltonian and characteristic extraction and correlate with gate performance. Turn that knowledge into actionable feedback for device design, fabrication, and control hardware teams, and drive those changes to closure.

• Prepare novel Rigetti devices for use by internal applications development teams and external deployment.

• Stay current with the literature and convert state-of-the-art techniques into working capability on production hardware.

• Contribute to the field of superconducting quantum computing by converting relevant findings into high-quality publications.

Required Qualifications

• PhD in Physics, Applied Physics, Electrical Engineering, or a related field.

• Significant hands-on experience calibrating and characterizing two-qubit gates on superconducting quantum devices; direct experience with tunable couplers is a strong plus.

• Deep understanding of gate design, pulse engineering, and decoherence mechanisms, with a track record of connecting error diagnostics to concrete fidelity improvements.

• Demonstrated ability to independently execute complex experimental efforts from concept to validated result.

• Strong Python skills in a scientific context, and comfort building tools that others rely on.

• Dogged experimental determination, with the judgment to balance depth of investigation against speed of iteration.

• Excellent communication skills and a team-first mindset in a strongly collaborative environment.

Nice to Have

• Experience with quantum simulation frameworks such as QuTiP for gate and noise modeling.

• Experience deploying calibration or benchmarking procedures across large multi-qubit processors in an industrial or startup setting.

• Familiarity with randomized benchmarking variants, gate set tomography, cycle benchmarking, or other scalable error diagnostics.

• Publication record or demonstrated results in high-fidelity entangling gates, error suppression, or quantum control.

• Experience mentoring junior scientists or leading small technical teams.