CPU Physical Design Engineer - Full Time
Confirmed on the employer's own hiring board on Oct 30, 2026. First seen by Alion on Oct 5, 2026.
What you'll do
Analyze CPU microarchitecture (pipeline stages, execution units, cache hierarchy, branch prediction) to guide implementation tradeoffs on timing, power, and area
Develop and own gate-level design for CPU blocks: standard-cell selection, logic restructuring, and clock-domain/reset architecture
Perform transistor-level design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)
Drive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure
Own static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff
Debug and close timing, power, and DRC/LVS violations across corners and modes
Collaborate with RTL design, DFT, verification, and package/system teams to co-optimize PPA (power, performance, area)
Develop and improve physical design flows, scripts, and methodologies to boost QoR and turnaround time
Participate in design reviews, correlate silicon results with pre-silicon predictions, and drive root-cause debug of PPA gaps
What we're looking for
Master's degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of industry experience in CPU or high-performance ASIC physical design
Strong understanding of CPU microarchitecture: pipelines, out-of-order execution, caches, branch prediction, and interconnect
Hands-on experience with gate-level design, including standard-cell logic design and clock/reset architecture
Working knowledge of transistor-level/custom circuit design for high-speed and low-power structures
Proven track record driving synthesis and place-and-route (P&R) to timing, power, and area closure on complex blocks
Solid grasp of static timing analysis (STA), signal integrity, and physical verification (DRC/LVS)
Proficiency with industry-standard EDA tools for synthesis, P&R, and signoff (see Tools & Technologies)
Scripting proficiency in Tcl, Perl, or Python for flow automation
Strong analytical and debugging skills, with the ability to work through cross-corner, cross-mode PPA tradeoffs