SOC RTL Design Engineer

Position Summary

With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

As one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Role and Responsibilities

Will be part System Architecture and Design team and primarily responsible for IP/BLK level RTL integration and design of IP/glues/wrappers which involves complex high-speed protocol integration and support cross-functional teams (DV, DFT, PD).

Shall be responsible for handling the collaterals/reviews of cross-functional teams such as (but not limited to) i) Test plan/coverage reviews ii) Synthesis/Constraints QC iii) DFT insertion, HIP, SCAN strategies and QC at RTL level et al

Required Skills:

• Hands on experience in Front end RTL design, Integration, architecture, coding at IP Level.
• Domain Experience in the field of High Speed Serdes design is preferred. (Any one or more of following sub-domains) 1) The domains include : Storage (USB, UFS), High-Speed (PCIe, Ethernet), Display/Multi-media (CSI, DSI, eDP), Memory (LPDDR, HBM) 2) Good protocol understanding on standard interfaces such as : MIPI (CD, M-PHY), DFI Protocols and AMBA
• Hands-on experience on tools - LINT/VCLP/CDC/RDC/SYNTHESIS/Meggalan are must have skills.
• Should be able to handle - Design Constraints (SDC) at IP/BLK or flat level and respective QC flows.
• Additional tool knowledge on AFL/XPROP/DFT added advantage
• Good scripting skilss - Any scripting language (Perl, Python, TCL)

Skills and Qualifications

Experience - 4 to 7 years

Qualifications

• B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.