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Salary
$115k – $213k per year
Location
In office (San Jose)
Seniority
Staff
Employment
Full-Time
Overview
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Semiconductor Engineering is a technical media and research organization based in San Jose, California, and founded in 2013. The company provides in-depth news, analysis, and technical papers focused on the design, manufacturing, testing, and integration of advanced semiconductor technologies. It operates as a global information hub for chip engineers and industry professionals, offering newsletters, webinars, and specialized research reports.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This R&D engineer role is part of the timing optimization group of Cadence’s Innovus Place & Route product. This key Innovus R&D group is responsible for optimizing timing (how fast a chip functions) and power (the power consumption of the chip), and the timing closure flow. The Innovus product is a key product used by a variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, & AI. The work done in this high-performance team has a huge impact on the chip industry and products that are used in our daily lives.

We are looking for talented candidates with a strong background in electronic design automation (timing, power analysis, optimization), and excellent software engineering skills, experience with multithreaded and distributed optimization. We are looking for individuals that can make the next breakthrough in the technology that we provide to the customers, making a big impact to the industry.

Minimum Qualifications:

Highly technical engineer with excellent problem solving skills

C/C++ software development experience in Linux environment

Strong understanding and extensive usage of data structures and algorithms

Great communication skills and a strong desire for working with customers

MS (Ph.D. track a plus) in Electrical Engineering, Computer Science.

Preferred:

Knowledge of physical synthesis algorithms, timing analysis and multithreading is a strong plus.

Prior R&D experience working on IC physical designs tools

Hands on experience using the above physical design tools for design closure and knowledge of physical design flows a plus.

Experience with Tcl and other scripting languages

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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