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SemiWiki is an open community-driven semiconductor web portal and knowledge-sharing platform dedicated to the global electronic design automation (EDA) and semiconductor manufacturing industries. Founded in 2010 by industry veterans Daniel Nenni, Paul McLellan, and David Manners, SemiWiki provides analysis, expert blogging, and commentary on advanced node semiconductor technology, chip design methodologies, foundry economics, and supply chain dynamics.

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.

Job Description:

The Role:

We are seeking a JVM Performance Specialist to serve as the technical authority for managed runtimes on our RISC-V IP architecture. You will deep dive into JVM internals (JIT compilation, runtime execution, and garbage collection) to identify and resolve critical performance bottlenecks across pre-silicon, FPGA, and production environments.

By collaborating with our Compiler Team to optimize JIT code generation and fine-tuning GC algorithms, you will directly impact system scalability, throughput, and latency. This role goes beyond high-level tuning to bridge the gap between Java software execution and cutting-edge RISC-V hardware, ensuring our IP delivers peak performance for enterprise-critical workloads.

Responsibilities:

  • Profile and analyze core datacenter workloads to pinpoint inefficiencies in CPU utilization, memory hierarchy, I/O throughput, and network interactions within distributed and containerized environments.

  • Establish benchmarking methodologies and performance regression testing frameworks to ensure consistent execution quality of Java-based services on RISC-V.

  • Act as the primary expert in diagnosing and resolving performance friction within the Just-In-Time (JIT) compiler and the HotSpot runtime environment.

  • Collaborate closely with the Compiler Team to drive improvements in JIT code generation, ensuring the JVM effectively leverages the unique features of the RISC-V ISA.

  • Optimize JVM parameters to achieve industry-leading latency and throughput.

  • Translate performance data into actionable insights for hardware architects, helping to influence future RISC-V IP design to better support managed runtime environments.

Requirements:

  • Multiple years of experience with JIT compiler, runtime execution engine, and memory management subsystems.

  • Experienced with profiling tools such as perf, ftrace, eBPF, and async-profiler.

  • Proficiency in C/C++ and a strong understanding of modern CPU microarchitecture (pipeline execution, branch prediction, and memory consistency models).

  • Mastery of assembly (RISC-V, x86, or ARM) and the ability to analyze JIT-generated machine code to identify sub-optimal execution patterns.

  • (Nice-to-Have) Experience optimizing large-scale Java frameworks (e.g., Cassandra, Hadoop) within containerized or cloud-native environments.

  • (Nice-to-Have) Proven track record of tuning and optimizing GC algorithms (e.g., G1GC, ZGC, Shenandoah) to solve complex latency and throughput issues.

  • (Nice-to-Have) Familiarity with industry-standard benchmarks such as SPECjbb, or DaCapo, and the ability to derive meaningful insights from them.

If you want to do incredible work and be challenged by exciting, truly innovative projects that will test the boundaries of your skills and creativity, then SiFive is the place for you! Be proud of your work. Do things better. Join SiFive.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Taiwan

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

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