Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification)
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
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Job Description:
Responsibilities
Own verification planning and execution for ALU, floating-point blocks focussing on formal and datapath verification of these blocks.
Drive verification strategy, test planning, debug, coverage analysis, and closure for complex Vector, ALU, FPU execution-pipeline and datapath behaviours.
Define effective verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exception, and execution-to-commit interactions.
Develop robust verification environments, assertions, checkers, scoreboards, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
Partner closely with architecture, design, and verification teams to review specifications, identify risk early, and improve verification completeness.
Drive efficient root-cause debug across specification, RTL, tests, and verification infrastructure.
Contribute reusable methodology, automation, and infrastructure that improve verification quality and productivity across future CPU core programs.
Minimum Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
Solid understanding of computer architecture and CPU microarchitecture.
Experience verifying one or more of the following areas: ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.
Strong knowledge of verification flow methodology, including test planning, stimulus generation, debug, coverage analysis, and coverage closure.
Good scripting or programming skills in Python, C/C++, or similar languages used for DV infrastructure and automation.
Preferred Qualifications
Experience with high-performance out-of-order CPU core verification.
Experience developing high-value assertions, checkers, and scoreboards for control-heavy or dependency-sensitive CPU behavior.
Experience applying formal verification to execution logic, control interactions, or datapath correctness.
Experience collaborating effectively across architecture, design, performance, and verification teams.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.