Sr. Staff Engineer, Physical Design - Caches
Confirmed on the employer's own hiring board on Nov 13, 2026. First seen by Alion on Nov 13, 2026. SiFive scores A on the Alion truth index.
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.
Job Description:
About the Role --
At SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Sr. Staff Physical Design Engineer (Caches/Memory Subsystems), you will own the physical implementation of critical memory cache structures and tightly integrated SRAM subsystems, from RTL to GDSII. You will deliver high-performance, dense, and power-efficient memory designs on advanced and legacy process nodes.
While your primary focus will be in physical design, we are looking for engineers capable of operating across design-abstraction layers. Caches are the heart of CPU performance, and you will act as a bridge between the architecture, RTL, and implementation teams. By understanding the underlying design, you will help drive co-design optimizations that directly impact the speed, area, and efficiency of our IP.
Responsibilities - What you’ll do
Own Cache Implementation: Drive the physical design implementation for high-performance cache blocks and memory sub-systems, managing synthesis, place & route, and signoff.
Engage in Cross-Abstraction-Layer Co-Design: Go beyond standard implementation by actively participating in Architecture/RTL/Implementation co-design. Understand the cache micro-architecture to suggest RTL tweaks, pipeline strategies, or custom macro arrangements etc. that resolve physical bottlenecks.
Solve Memory-Specific Challenges: Tackle physical bottlenecks unique to cache design, including highly dense SRAM macro placement, complex routing over macros, critical path timing through memory arrays, and strict dynamic/leakage power management.
Aggressive PPA Optimization: Optimize block-level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex trade-offs for various product lines.
Collaborate Cross-Functionally: Work closely with RTL designers, IP vendors, and power teams to close design requirements and ensure efficient integration of memory instances.
Enhance Methodology: Support and improve physical design flows, automation scripts, and methodologies for memory-heavy block implementation.
Requirements - What you’ll bring
13+ years of hands-on experience in physical design implementation of PPA critical blocks (CPUs, Caches etc.).
Cross-Abstraction Awareness: A solid understanding of digital logic design and basic memory architecture. You should be comfortable reading RTL to understand the design intent and collaborate effectively with front-end teams.
Strong Problem Solving: Proven ability to optimize for aggressive PPA targets using industry-standard physical design techniques, accompanied by a detail-oriented mindset.
Tool Proficiency: Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence synthesis, PnR and signoff implementation tools. And good scripting skills. Tool Proficiency: Expertise in RTL to GDS flow implementation using Synopsys and/or Cadence tools for synthesis, Place and Route (PnR), and signoff.
Education: Bachelor’s or Master’s in Electrical or Computer Engineering.
Why join us?
Be part of the RISC-V movement and help define the future of computing architecture.
Work on industry-leading IP adopted by top customers and shipped in high volumes worldwide.
Collaborate with world-class engineers in a supportive, fast-paced, learning environment.
Enjoy a culture that values innovation, ownership, and technical excellence.
Our large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.