Zebu flow Engineer
Confirmed on the employer's own hiring board on Oct 15, 2026. First seen by Alion on Aug 3, 2026. SiFive scores A on the Alion truth index.
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.
Job Description:
The Role:
The successful candidate will join SiFive's System Validation team, which is responsible for the building flow for modelling SiFive's RISC-V CPUs on Emulators like Synopsys Zebu. This role extends beyond Emulators and will work with other FPGA based platforms and flows. .
This position offers significant exposure to RISC-V processors, the RISC-V software ecosystem, and various development boards, providing exceptional learning opportunities for engineers pursuing a career in the RISC-V domain.
Responsibilities
Build and maintain a modular flow for building Synopsys ZeBu models using the SiFive internal build system. This includes transitioning compilation steps into the SiFive wake-based build environment to support seamless integration with other internal flows.
Execute root cause and failure analysis across RISC-V CPU hardware and software components.
Facilitate debug using ZeBu features like waveform dumping and utilize ILA and JTAG debuggers to troubleshoot and validate designs.
Develop failure hypotheses through systematic, step-by-step elimination of potential causes.
Create and support Python-based scripts to enhance and automate debug workflows, and support the integration of ZeBu runtime automation into the SiFive manager ecosystem.
Work cross-functionally and maintain active partnership with both the software and validation engineering departments.
Requirements:
1+ years of experience with a Bachelor’s or Master’s degree in Computer Science or Electronics and Communication Engineering is required.
A strong understanding of logic design is essential.
Prior exposure to logic design using Verilog and the subsequent porting of designs onto FPGA platforms is necessary.
Practical experience with Linux-based operating systems and scripting languages such as Python and BASH is mandatory.
Candidates must possess a positive attitude, a proactive approach to continuous learning, and a commitment to achieving excellence in their work.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.