Senior STA Engineer
Confirmed on the employer's own hiring board on Oct 21, 2026. First seen by Alion on Oct 8, 2026.
Oversee sub-system/complex block-level STA convergence from early stages to signoff.
Take part in sub-system/complex block-level floorplan and clock planning.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes including their optimization of runtime.
Manage schedules, and risk tracking for STA deliverables.
Prepare and present project status, risk and mitigation plans to leads and customer.
Work effectively in large teams with multiple vendors.
Requirements
4-8 years of experience in ASIC/SOC STA.
Strong experience in ASIC timing constraints generation, validation and timing closure.
Expertise in Tempus/Primetime and timing eco (physical aware) using Tempus ECO/PT-DMSA/Tweaker - sub-system level and block-level.
Experience in IO Timing/interface budgeting/process margins/corner definitions
Familiarity with DFT.
Proficient in scripting language (TCL/python).
Excellent timing and flow debugging skills.
Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence.
Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.
Proficient in scripting language (TCL/python).
Hands on experience in reference flows, excellent debugging skills.