Analog Design, Staff Engineer
Job Description and Requirements
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are
You have spent years in the trenches of high-speed interface design, where a 50-ohm trace matters and a poorly modeled via can sink a product launch. You know that signal integrity is not just about making the eye diagram look clean, it is about understanding what breaks at 56 Gbps and why the power delivery network you signed off on three months ago is now causing headaches in the lab. You think in transmission lines, S-parameters, and frequency domain responses, not because you memorized the textbook but because you have debugged enough real silicon to know where theory meets reality.
You are comfortable sitting with a layout team reviewing a PCB stackup, then jumping into a SPICE deck to model crosstalk on a DDR5 interface, then explaining to a customer why their return path is the problem. You do not wait for someone to hand you a perfect model. You build it, verify it, and iterate until it matches what you see on the scope.
Research excites you, especially when it is tied to what is coming next. MRDIMM, LPDDR6, HBM4, UCIe. You want to be ahead of the curve, not chasing it. At Synopsys, you will work on the interfaces that power the next generation of AI and compute, and the work you do will show up in customer tape-outs across the industry.
What You'll Be Doing
- Review and analyze die, package, and PCB physical layouts for signal integrity and power integrity performance on high-speed interfaces
- Model, simulate, and verify DDR, HBM, UCIe, PCIe, and Ethernet interfaces using SPICE and 3D field solvers to ensure compliance with specifications
- Drive improvements to SI/PI methodology flows, identifying bottlenecks and building automation to increase accuracy and turnaround time
- Collaborate with IP development, customer engagement, and CAD teams on cross-functional projects tied to next-generation interface rollouts
- Independently lead SI/PI research and development activities for emerging standards including MRDIMM, LPDDR6, HBM4, and UCIe
- Debug and resolve signal integrity and power integrity issues in customer SoC, package, and board designs across different application domains
- Script and automate simulation workflows using Python and TCL to streamline repetitive tasks and improve team productivity
The Impact You Will Have
- Enable SI/PI sign-off for customer designs across automotive, data center, mobile, and AI applications, directly affecting tape-out schedules and product success
- Improve the speed and accuracy of SI/PI methodology flows used by teams globally, reducing simulation turnaround time and increasing confidence in results
- Provide technical guidance to customers on next-generation memory and interconnect IP, helping them navigate design tradeoffs before they commit to silicon
- Drive early research into emerging standards so Synopsys can deliver IP and tools ahead of industry adoption curves
- Build cross-team collaboration between Bengaluru, North America, and APAC engineering groups, ensuring knowledge transfer and consistent methodology
- Contribute to Synopsys' leadership in high-speed interface IP by solving hard problems that competitors have not figured out yet
- Support the development of AI-driven SoCs by ensuring the memory and interconnect layers can actually deliver the bandwidth the architecture promises
What You'll Need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
- 5+ years of hands-on experience in signal integrity, power integrity, or high-speed interface design
- Strong working knowledge of transmission line theory, time-domain and frequency-domain analysis, and S-parameter modeling
- Proficiency with SPICE simulation tools and experience using 3D electromagnetic field solvers for layout extraction and analysis
- Practical understanding of DDR, HBM, UCIe, PCIe, or Ethernet interface architectures and their SI/PI challenges
- Solid verbal and written communication skills in English, you will work with global teams and customer-facing engineers regularly
- Experience with Python and TCL scripting for simulation automation and data post-processing is a strong plus
Who You Are
- You can look at a layout and immediately spot the return path discontinuity or the stub that is going to cause reflections at 10 GHz
- You are comfortable explaining a complex SI tradeoff to a customer architect in two sentences without losing the technical nuance
- You do not treat simulation as a black box, if the results do not make sense, you dig into the model until you understand why
- You are organized enough to juggle multiple customer engagements and internal projects without dropping threads or missing deadlines
- You push back when a design decision does not make sense from an SI/PI perspective, and you do it with data, not opinion
- You are curious about what is coming next in the industry and you actively read specs, papers, and early drafts of emerging standards
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.