DFT Engineer

• Responsible for scan insertion, MBIST, ATPG for SOC based design using industry standard EDA tools.
• Generate test vectors, analyze and improve test coverage, reduce test time and test cost.
• Perform pre/post-layout scan and MBIST simulations.
• Work with designers on STA, physical, power and logical issues related to DFT.
• Work with test engineers to bring up all test patterns before production test release.

Requirements

• Bachelor/Master Degree in Electronics & Communication

  Engineering and at least 5 years of experience in DFT implementation.

• Skilled in different types of DFT structures,

  including scan (Stuck-At, At-Speed, Path-Delay), scan test compression,

  boundary scan and MBIST.

• Understanding of timing concept and working with

  STA engineer on timing related issues.

• Running pre/post layout simulation on test

  patterns.

• Experience in test time and test coverage analysis for scan and

  MBIST patterns.

• Ability to perform test time and test coverage analysis for scan and

  MBIST pattern to improve performance.

• Experience working with test engineering to bring up the test

  program for production testing.