(竹北) DRAM Controller Architect
Confirmed on the employer's own hiring board on Oct 30, 2026. First seen by Alion on Oct 29, 2026.
作為華邦的(竹北) DRAM Controller Architect ，你將負責替客戶設計符合需求的電路圖，與製程研發/CAD/產品測試/FAE等團隊合作，完成重要專案。工作內容包含： ，以下為工作內容、工作條件以及重要通知。
工作內容
1. Architecture definition
2. Functional requirement and interface specification development
3. Performance, power, latency, and reliability analysis
4. Technical and design review leadership
5. Coordination across RTL, verification, analog, and physical design teams
工作地點：竹北辦公室(新竹縣竹北市文興路二段539號)
聘僱性質：全職
條件要求
學歷要求：碩士
科系要求：電機電子工程相關 │ │
相關經驗：10年以上
語言能力：英文 優級 │ │
管理責任：No
輪班需求：No
出差需求：1個月以下
外派需求：No
其他條件：
1. Strong background in memory controller, DDR/LPDDR PHY, or high-speed interface architecture
2. Ability to develop architecture and design specifications
3. Strong technical communication skills
4. DDR/LPDDR standards, memory-system performance analysis, technical leadership, or silicon bring-up experience preferred
5. Fluent English speaking and listening skills