Overview
News
Technologies
Salaries
Products
People
Growth
Jobs
Financials
Overview
SemiWiki is an open community-driven semiconductor web portal and knowledge-sharing platform dedicated to the global electronic design automation (EDA) and semiconductor manufacturing industries. Founded in 2010 by industry veterans Daniel Nenni, Paul McLellan, and David Manners, SemiWiki provides analysis, expert blogging, and commentary on advanced node semiconductor technology, chip design methodologies, foundry economics, and supply chain dynamics.
News
Using Claude AI for Chip Design
After speaking with dozens of semiconductor professionals at the Design Automation Conference in Long Beach about AI in the chip-design workflow, Claude emerged as the common denominator in every conversation. We're still at the tip of the iceberg when it
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Report
RVA23 Ends Speculation's Monopoly in RISC-V CPUs - Semiwiki
RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no
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Report
CEO Interview with Brandon Lucia of Efficient Computer - Semiwiki
Brandon Lucia is the CEO and co-founder of Efficient Computer, the company building the world's most energy-efficient general-purpose processors, and a Full Professor in the department of electrical and computer engineering at Carnegie Mellon University.
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Report
Silicon Valley, à la Française - Semiwiki
Since the fall of the Roman Empire, France has played a defining role in shaping Western civilization. In the 9th century, Charlemagne-a Frank-united much of Europe under one rule, leaving behind a legacy so profound he is still remembered as the
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Report
CHIPS Act dies because employees are fired - NIST CHIPS people are probationary - Semiwiki
- NIST to lose 100
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Report
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Technologies
Tech DNA
SystemVerilog
Python
Verilog
UVM
Django
CUDA
PostgreSQL
Redis
AWS
Amazon S3
Amazon EC2
LLM
AI/ML
Python
Scala
C++
SQL
Git
GitHub
CI/CD
CMake
LLVM
Vector
PyTorch C++
Platform Engineering
AWS
Docker
Jenkins
Kubernetes
QEMU
Amazon S3
CUDA
CUDA Toolkit
PyTorch
TensorFlow C++
Amazon EC2
Amazon EKS
AWS Lambda
Concourse
GitHub Actions
Helm
Terraform
Debian
Red Hat
Grafana
eBPF
IAM
HPC
PostgreSQL
Redis
RAG
ONNX
OpenMP
TensorFlow
LLM
OpenCL
SGLang
Triton
vLLM
Hadoop
ROCm
TGI
Model Context Protocol
AI Agents
Edge AI
Hardware
SystemVerilog
Verilog
Chisel
VHDL
Bluespec
Rust
C
Ada
UVM
Formal Verification
FIRRTL
Synopsys SpyGlass
Synopsys Verdi
U-Boot
OpenOCD
JTAG Debuggers
Cadence JasperGold
Synopsys VC Formal
Cadence Innovus
Synopsys Fusion Compiler
Synopsys Formality
Synopsys IC Compiler II
Synopsys PrimeTime
QA
JavaScript
Java
Groovy
TypeScript
Go
Pytest
Robot Framework
Other
Perl
Haskell
Jira
Confluence
Django
Rest API
React.js
Stack modernity
72/100
How modern this stack is, based on technology relevance, AI adoption and the share of legacy tools.
In-demand technologies
SystemVerilog
47 jobs
Required
$219k
Median
Python
34 jobs
Required
$227k
+26% vs market
Verilog
32 jobs
Required
$219k
+12% vs market
Chisel
31 job
Required
$219k
Median
Scala
29 jobs
Required
$219k
+24% vs market
UVM
27 jobs
Required
$223k
+2% vs market
C++
19 jobs
Required
$219k
+9% vs market
Formal Verification
18 jobs
Required
$283k
+17% vs market
Salary medians are calculated from this company's open jobs and compared with the market.
Industry adoption
Python
18%
SQL
14%
CI/CD
14%
JavaScript
13%
AWS
13%
Docker
12%
Share of companies in the same industry that use each technology.
Stack changes
Edge AI
Aug 2026
HPC
Aug 2026
AI Agents
Aug 2026
Model Context Protocol
Aug 2026
IAM
Aug 2026
Amazon S3
Aug 2026
GitHub
Aug 2026
TGI
Aug 2026
Technologies recently added to or removed from this company's stack - a signal of tech migrations and new initiatives.
NVIDIA
Qualcomm
Weekday
Jobgether
Bosch
NXP Semiconductors
Salary insights
Compensation ranges based on this company's open jobs
Median
$219k
Typical range
$171k – $311k
Open positions
15
14
Jobs
Middle
28.6%
Senior
21.4%
Staff
21.4%
Principal
14.3%
Architect
14.3%
| Level | Jobs | Median | Typical range |
|---|---|---|---|
| Middle | 4 | $206k | $171k – $251k |
| Senior | 3 | $194k | $194k – $219k |
| Staff | 3 | $251k | $219k – $251k |
| Principal | 2 | $283k | $283k |
| Architect | 2 | $297k | $283k – $311k |
Highest paying role
SOC Architect
$311k
Normalized to USD per year
Growth
Hiring Momentum
72/100
Growing
Open positions
76
9 opened / 6 closed in 30 days
Median time-to-fill
36 days
faster than 39% of the market
ATS activity
Every ~4 hours
08/30/2026
Hiring Dynamics
+100%
Hiring Focus
The percentage next to each role is its share of the company's job openings over the last 90 days; the arrow shows the shift versus the previous period.
Hardware
67% ▼
DevOps
16%
Backend
7% ▲
QA
5% ▲
Frontend
2% ▼
Product
2% ▲
Actively hiring for Hardware (+15 in 30 days)
Activity Timeline
New location: La Ciotat
Aug 2026
New location: Washington
Aug 2026
New location: Georgia
Aug 2026
New location: Belgium
Aug 2026
New location: Austria
Aug 2026
Added Edge AI to stack
Aug 2026
Added HPC to stack
Aug 2026
Added AI Agents to stack
Aug 2026
Added Model Context Protocol to stack
Aug 2026
Added IAM to stack
Aug 2026
Added Amazon S3 to stack
Aug 2026
Added GitHub to stack
Aug 2026
Jobs
Power Infrastructure Lead
3 days ago$206k – $251k per year • In office • Full-Time • 5+ years exp • Master's Degree • Santa Clara • Hsinchu • Austin • Bengaluru • Berkeley
Apply
Senior ALU Design Engineer
5 days agoRemote/Hybrid • Full-Time • 2+ years exp • Master's Degree • Cambridge
Chisel
SystemVerilog
Verilog
VHDL
Apply
Lead Debug/Trace/Profiling Design Engineer
5 days agoIn office • Full-Time • 7+ years exp • Master's Degree • Cambridge • Austin • Boston
Chisel
Scala
SystemVerilog
Verilog
VHDL
Git
Chips/EDA
FIRRTL
Management
Confluence
Jira
Apply
Debug/Trace/Profiling Design Engineer
5 days agoIn office • Full-Time • 7+ years exp • Master's Degree • Cambridge • Austin • Boston
Chisel
Scala
SystemVerilog
Verilog
VHDL
Git
Chips/EDA
FIRRTL
Management
Confluence
Jira
Apply
Staff Engineer - Formal Verification
5 days agoIn office • Full-Time • 8+ years exp • Bengaluru
Chisel
SystemVerilog
Verilog
VHDL
Cadence JasperGold
Formal Verification
Synopsys VC Formal
Apply
Staff Engineer
5 days agoIn office • Full-Time • 7+ years exp • Bachelor's Degree • Ahmedabad
Python
SystemVerilog
Formal Verification
UVM
Apply
Interconnect Design Engineer
5 days agoIn office • Full-Time • Bachelor's Degree • Santa Clara • Cambridge • Austin • Boston
Bluespec
Chisel
Scala
SystemVerilog
Verilog
VHDL
Git
Chips/EDA
FIRRTL
Management
Confluence
Jira
Apply
Staff Engineer - DV
5 days agoIn office • Full-Time • 7+ years exp • Bachelor's Degree • Bengaluru
Python
SystemVerilog
Verilog
UVM
Apply
In office • Full-Time • Bachelor's Degree • Hyderabad
Perl
Python
SystemVerilog
Verilog
UVM
Apply
Staff Engineer - Design Verification
5 days agoIn office • Full-Time • 7+ years exp • Bachelor's Degree • Hyderabad
SystemVerilog
UVM
Apply
Principal Interconnect Design Engineer
5 days ago$231k – $283k per year • In office • Full-Time • Bachelor's Degree • Santa Clara • Cambridge • Austin • Boston
Bluespec
Chisel
Scala
SystemVerilog
Verilog
VHDL
Git
Chips/EDA
FIRRTL
Management
Confluence
Jira
Apply
Platform Technologies Language Design Intern
5 days agoIn office • Internship • Santa Clara • Berkeley
Chisel
Scala
Platform Engineering
Apply
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