Senior Director, Silicon Hardware Engineering - Boards, Packaging, & Reliability
Confirmed on the employer's own hiring board on Oct 19, 2026. First seen by Alion on Sep 10, 2026. Altera scores A on the Alion truth index.
Job Details:
Job Description:
About Altera
At Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
We are seeking a seasoned and technically deep engineering leader to serve as Senior Director of Silicon Hardware Engineering - Boards, Packaging & Reliability, leading a global, distributed organization spanning chip package development, board hardware development, and silicon power and reliability engineering. Reporting directly to the VP of Engineering, this leader will be accountable for defining and executing the technical strategy, development methodologies, and organizational capabilities required to deliver high-performance, reliable silicon hardware solutions at scale. The ideal candidate combines hands-on technical expertise and sound engineering judgment in advanced semiconductor technologies with a proven track record of operational excellence, cross-functional collaboration, and building and leading high-performing engineering organizations across U.S. and Asia sites.
Key Responsibilities
Team & Organizational Leadership
Lead,develop, and scalethree core engineering functions: chip package development, board hardware development, and silicon power and reliability engineering.
Build, mentor, and develop high-performing engineering teams distributed across the U.S. and Asia, fostering a collaborative,accountable, andresults-driven culture.
Partner closely with VP/SVP leadership to define multi-yeartechnicalroadmaps, headcount plans, and organizational strategy.
Establish clear goals, KPIs,engineering standards,and performance expectations across all teams.
Drive technical and organizational alignment across the three functions to improve execution, quality, and predictability across product programs.
Technical Excellence
Define and drive technical direction foradvanced package technologies including 2.5D/3D IC, flip-chip, and high-density interconnect.
Oversee board-level hardware development from concept through bring-up, ensuring design-for-manufacturability and design-for-test.
Champion rigorous signal integrity (SI) and power integrity (PI) methodologies, ensuringconsistent engineering standards andadoption of best-in-class EDA tooling across teams.
Lead silicon power and reliability programs including power budgeting, electromigration, ESD, and reliability qualification.
Apply deep knowledge of silicon design development methodologies to improve tapeout quality, schedule, and first-pass silicon success rates.
Drive disciplined technical reviews and engineering decision-making across package, board, SI/PI, power, and reliability activities to identify and mitigate product risks early.
Program Execution, Operations & Vendor Management
Own end-to-endengineeringprogram execution across multiple concurrent programs, driving on-time and on-budget delivery.
Develop and execute cost-reduction strategies across packaging, board materials, and test processes without compromising qualityor product requirements.
Manage complex, multi-vendor relationships with OSATs, PCB fabricators, substrate suppliers, and EDA vendors.
Implement robust supplier qualification, scorecard, and escalation processes to ensuresupplier performance andsupply chain resilience.
Drive continuous improvement in cycle time and cost through data-driven operational reviews.
Establish clear execution metrics, risk-management mechanisms, and escalation paths to improve predictability across development programs.
Cross-Functional & Executive Leadership
Serve as the primary engineering interface for internal customers including silicon architecture, SoC design, system integration, and product management teams.
Partner across engineering functions to ensure package, board, power, reliability, and silicon development requirements are aligned throughout the product-development lifecycle.
Represent hardware engineering in executive reviews, customer engagements, and technology partnership discussions.
Communicate complex technical tradeoffsand associated cost, schedule, quality, and product implicationsclearly to non-technical stakeholders and senior leadership.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$231,500 - $335,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or closely related field required; Master's Degree preferred.
15+ years of progressive experience in semiconductor hardware engineering, with at least 5 years in a senior leadership or director-level role.
Demonstrated experience managing global, cross-functional engineering teams across U.S. and Asian sites.
Deep technical expertise in chip package development, including advanced packaging, substrate design, and OSAT management.
Proven experience in chip board hardware development, including schematic design, PCB layout, and bring-up.
Strong hands-on background in signal integrity and power integrity analysisand methodologies, including experience with industry-standard tools such as Ansys SIwave, Cadence Sigrity, HyperLynx, or equivalent.
Solid understanding of silicon design development methodologies, including synthesis, place and route (P&R), timing closure, and DFT.
Track record of delivering measurable cost-reduction programs across package and board hardwarewhile maintaining product quality and technical requirements.
Experience managing and qualifying multiple external vendors and OSATs simultaneously.
Demonstrated ability to drive complex engineering programs and technical decisions across organizational boundaries.
Excellent communication,influencing,and executive presentation skills.