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Senior Product Development Engineer

Altera • Processors, MCUs & AI Chips • Bachelor's Degree • 5 hours ago
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Salary
≈ $21k – $48k per year (Estimated)
Location
In office (George Town)
Seniority
Senior
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 1, 2026. First seen by Alion on Oct 1, 2026. Altera scores A on the Alion truth index.

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Altera

Altera is an American programmable logic company whose field programmable gate array business was founded in 1983, acquired by Intel in 2015 and separated again as a standalone company in 2025 when the private equity firm Silver Lake took a majority stake. It designs FPGAs and structured application specific integrated circuits used where a design must be reconfigurable after manufacture, which makes them common in communications infrastructure, industrial control, automotive, aerospace, defence and test equipment. Headquartered in San Jose, the company sells its Agilex and Cyclone device families alongside the Quartus design software engineers use to program them.
altera.com • HQ: San Jose, Santa Clara, United States • Processors, MCUs & AI Chips • 1001-5000 employees • Est. 1983
Tech stack of Altera

Job Details:

Job Description:

The Product Development Engineer is responsible for developing and deploying manufacturing test solutions for advanced FPGA products, from test architecture definition through production release. You will work closely with Design, DFT, Product Engineering, Manufacturing, and Software teams to ensure high-quality, cost-effective, and manufacturable test solutions throughout the product lifecycle.

Key Responsibilities

  • Develop full-chip test methodologies and manufacturing test solutions for FPGA products.
  • Define and verify on-chip Design-for-Test (DFT) structures and test strategies.
  • Generate test vectors, perform coverage analysis, and drive test quality improvements.
  • Develop, debug, and validate Automated Test Equipment (ATE) programs for production manufacturing.
  • Support first silicon bring-up, debug, and production ramp activities.
  • Collaborate with global cross-functional teams including Design, DFT, Software, Product Engineering, and Manufacturing teams throughout product development.
  • Analyze test results, yield loss, and failure data to identify root causes and implement corrective actions.
  • Drive test optimizations to reduce test cost, improve manufacturing efficiency, accelerate production stability, and enhance product quality.
  • Develop and maintain HMDT & UFP test modules and related test infrastructure.
  • Convert test patterns from STIL format to production-ready pattern objects (POBJ).
  • Perform tester validation, correlation, and production readiness qualification.
  • Support yield improvement, test program conversion, and continuous improvement initiatives.

Qualifications:

  • Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
  • Experience in semiconductor test development, product engineering, DFT, or manufacturing test environments.
  • Strong understanding of digital circuit fundamentals and semiconductor testing methodologies.
  • Knowledge of DFT concepts, including Scan, ATPG, MBIST, JTAG, and Boundary Scan.
  • Experience with test vector generation, test coverage analysis, and silicon debug.
  • Familiarity with ATE platforms and test program development.
  • Strong analytical and debugging skills.
  • Excellent communication and teamwork skills.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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