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DFT Engineer Intern

Ambarella • Artificial Intelligence • Hardware • Verilog • 1 month ago
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Salary
≈ $89k – $256k per year (Estimated)
Location
In office (United States)
Seniority
Intern
Employment
Internship

Confirmed on the employer's own hiring board on Sep 27, 2026. First seen by Alion on Aug 27, 2026. Ambarella scores B on the Alion truth index.

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Ambarella

Ambarella's advanced imaging solutions make cameras smarter by extracting valuable data from high-resolution video streams.
ambarella.com • Shanghai • Shenzhen • Hsinchu • Hardware • Artificial Intelligence • Processors, MCUs & AI Chips
Tech stack of Ambarella

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Position Responsibilities:

  • Logic Design to support DFT features
  • Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC
  • Verification of DFT Logic and analysis of fault coverage
  • Timing analysis for DFT Modes

Minimum Requirements:

  • MSEE in Electrical / Computer Engineering
  • Knowledge of DFT fundamentals
  • Knowledge of Logic design & Static timing analysis
  • Knowledge of Verilog and any scripting language
  • Knowledge of AI assisted programming
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