PD Clocking Engineer

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Role Summary

Own and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Responsible for developing, validating, and maintaining implementation flows, clock-tree methodologies, timing correlation, QoR convergence strategies, and automation frameworks used across multiple projects.

Key Responsibilities

• Own end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies.
• Develop, certify, and maintain PnR implementation flows across technology nodes and design styles.
• Drive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure.
• Define implementation recipes, optimisation strategies, and best practices for timing, congestion, power, and area closure.
• Develop automation using Tcl/Python/Shell to improve productivity, debug efficiency, and flow robustness.
• Partner with CAD, FCFP, Timing, DFT, and Design teams to resolve methodology issues and improve project execution.
• Enable new technology nodes, validate EDA tool features, and drive methodology enhancements for future projects

Required Qualifications

• Bachelor's/Master's degree in Electrical/Electronics Engineering.
• Strong understanding of ASIC Physical Design flow including Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification.
• Expertise in clock-tree synthesis, clock skew/latency optimisation, and timing closure methodologies.
• Experience with industry-standard tools such as Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, and RedHawk.
• Strong scripting skills in Tcl, Python, and Shell.
• Good debugging, problem-solving, and cross-functional collaboration skills.

Preferred Experience

• Prior experience owning flow development, methodology certification, or automation projects.
• Experience across advanced technology nodes (5nm/3nm and below) is a plus.
• #LI-BM2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Role Summary

Own and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Responsible for developing, validating, and maintaining implementation flows, clock-tree methodologies, timing correlation, QoR convergence strategies, and automation frameworks used across multiple projects.

Key Responsibilities

• Own end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies.
• Develop, certify, and maintain PnR implementation flows across technology nodes and design styles.
• Drive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure.
• Define implementation recipes, optimisation strategies, and best practices for timing, congestion, power, and area closure.
• Develop automation using Tcl/Python/Shell to improve productivity, debug efficiency, and flow robustness.
• Partner with CAD, FCFP, Timing, DFT, and Design teams to resolve methodology issues and improve project execution.
• Enable new technology nodes, validate EDA tool features, and drive methodology enhancements for future projects

Required Qualifications

• Bachelor's/Master's degree in Electrical/Electronics Engineering.
• Strong understanding of ASIC Physical Design flow including Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification.
• Expertise in clock-tree synthesis, clock skew/latency optimisation, and timing closure methodologies.
• Experience with industry-standard tools such as Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, and RedHawk.
• Strong scripting skills in Tcl, Python, and Shell.
• Good debugging, problem-solving, and cross-functional collaboration skills.

Preferred Experience

• Prior experience owning flow development, methodology certification, or automation projects.
• Experience across advanced technology nodes (5nm/3nm and below) is a plus.
• #LI-BM2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.