Senior Staff Front End Automation Engineer
Confirmed on the employer's own hiring board on Oct 25, 2026. First seen by Alion on Sep 7, 2026. AMD scores B on the Alion truth index.
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.
THE ROLE:
We are seeking a senior Front-End Design Automation Engineer to help shape and advance our front-end EDA flows - RTL lint and design-quality checking, static timing analysis and constraints, and RTL quality (CDC/RDC) signoff. This senior individual-contributor role blends deep technical work with driving the flow roadmap, and a strong focus on modernizing front-end verification and signoff with AI - machine-learning and agent-based automation for faster, smarter, more autonomous flows.
KEY RESPONSIBILITIES:
- Help shape the technical direction and roadmap for the front-end flows (lint/design-quality, STA and constraints, RTL quality signoff), including architecture, enablement, and release strategy.
- Drive AI-based modernization - applying ML and agentic automation to lint triage, timing/constraint debug, and regression analysis.
- Serve as a technical resource and mentor for FE flow issues, ruleset decisions, and methodology questions from design teams.
- Drive user enablement and adoption - low-power (UPF) and timing-flow enablement, best-practice guidance, and documentation.
- Partner with design, CAD, IP, and library teams, and maintain regression/CI (e.g., nightly pipelines) for flow quality.
PREFERRED EXPERIENCE:
- Extensive experience in silicon design automation / front-end methodology / RTL flow development, with a track record of driving technical initiatives.
- Deep expertise in front-end flows: RTL lint/design-quality, static timing analysis and constraint (SDC) development, RTL quality signoff including CDC, and low-power (UPF).
- Strong understanding of the RTL-to-signoff flow and how front-end deliverables feed physical implementation.
- Proficient scripting (Tcl, Python, Perl) and comfortable with flow infrastructure and regression/CI (e.g., Jenkins).
- Hands-on with industry front-end EDA tools (Synopsys / Cadence - STA, lint, CDC).
- Strong communication and cross-functional collaboration across distributed teams.
- Experience applying AI/ML or LLM-based agents to EDA flows or design automation.
- FPGA / ASIC / SoC experience in advanced nodes; familiarity with Perforce/ICManage and central IP/library releases.
LOCATION:
Penang, Malaysia
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
We are seeking a senior Front-End Design Automation Engineer to help shape and advance our front-end EDA flows - RTL lint and design-quality checking, static timing analysis and constraints, and RTL quality (CDC/RDC) signoff. This senior individual-contributor role blends deep technical work with driving the flow roadmap, and a strong focus on modernizing front-end verification and signoff with AI - machine-learning and agent-based automation for faster, smarter, more autonomous flows.
KEY RESPONSIBILITIES:
- Help shape the technical direction and roadmap for the front-end flows (lint/design-quality, STA and constraints, RTL quality signoff), including architecture, enablement, and release strategy.
- Drive AI-based modernization - applying ML and agentic automation to lint triage, timing/constraint debug, and regression analysis.
- Serve as a technical resource and mentor for FE flow issues, ruleset decisions, and methodology questions from design teams.
- Drive user enablement and adoption - low-power (UPF) and timing-flow enablement, best-practice guidance, and documentation.
- Partner with design, CAD, IP, and library teams, and maintain regression/CI (e.g., nightly pipelines) for flow quality.
PREFERRED EXPERIENCE:
- Extensive experience in silicon design automation / front-end methodology / RTL flow development, with a track record of driving technical initiatives.
- Deep expertise in front-end flows: RTL lint/design-quality, static timing analysis and constraint (SDC) development, RTL quality signoff including CDC, and low-power (UPF).
- Strong understanding of the RTL-to-signoff flow and how front-end deliverables feed physical implementation.
- Proficient scripting (Tcl, Python, Perl) and comfortable with flow infrastructure and regression/CI (e.g., Jenkins).
- Hands-on with industry front-end EDA tools (Synopsys / Cadence - STA, lint, CDC).
- Strong communication and cross-functional collaboration across distributed teams.
- Experience applying AI/ML or LLM-based agents to EDA flows or design automation.
- FPGA / ASIC / SoC experience in advanced nodes; familiarity with Perforce/ICManage and central IP/library releases.
LOCATION:
Penang, Malaysia
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.