Staff Design Verification Engineer
Confirmed on the employer's own hiring board on Oct 21, 2026. First seen by Alion on Jul 1, 2026.
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.
STAFF VERIFICATION DESIGN ENGINEER
THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s micoprocessor IP, resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements
- Develop an automated regression infrastructure setup for functional verification of high-speed microprocessor designs
- Develop interface assertions and work closely with formal verification team
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Working experience of memory subsystems would be a plus
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using C++ testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- CPU pipeline knowledge
- Automating workflows in a distributed computeenvironment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience with SystemVeriloglanguage
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assetswith prior exposure to memory subsystem or other CPU unit verification
- 3+ years of experience in Design Verification
ACADEMIC CREDENTIALS:
- Bachelors or Mastersdegree in computer engineering/Electrical Engineering
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
STAFF VERIFICATION DESIGN ENGINEER
THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s micoprocessor IP, resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements
- Develop an automated regression infrastructure setup for functional verification of high-speed microprocessor designs
- Develop interface assertions and work closely with formal verification team
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Working experience of memory subsystems would be a plus
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using C++ testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- CPU pipeline knowledge
- Automating workflows in a distributed computeenvironment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience with SystemVeriloglanguage
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assetswith prior exposure to memory subsystem or other CPU unit verification
- 3+ years of experience in Design Verification
ACADEMIC CREDENTIALS:
- Bachelors or Mastersdegree in computer engineering/Electrical Engineering
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.