Design Verification Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for verifying complex digital IPs. Work with the system architects and digital designers, making block level specifications clear and precise. Use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions in blocks. Own the creation of the verification test benches using formal verification and UVM based simulation. Build the test cases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for blocks. Participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve our goal of bug free designs on the first tape out. Collaborate in developing precise design specifications for digital control blocks. Use design specifications to create block and chip level verification plans. Architect and create block level verification elements. Assist in architecting chips and system level verification environments. Use System Verilog and UVM to develop drivers, tests, reference models and checkers. Debug test failures and work with designers to develop fixes. Use functional and code coverage to track progress and gauge tape out readiness.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.

Experience and/or education must include:

Utilizing System Verilog to create block level verification elements

Utilizing Verilog, VHDL to debug design issues and to identify root causes on bugs

Utilizing Digital Hardware Simulation to develop checkers and tests

Utilizing Object Oriented Programming, C to understand and debug firmware executions on the chips

Utilizing Python, Perl, or algorithms to develop design verification automation flows

Utilizing Chip simulations on CAD software including debugging simulation failures for bug hunting

Utilizing Finite State Machine design and verification experience to fully verify the FSM design

Preferred Qualifications

N/A