Formal Validation Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.). Work with Apple Silicon’s world-class SOC and IP design engineers to develop formal micro-architecture specifications. Develop comprehensive verification test plans. Help improve micro-architecture by proving properties, finding bugs and performing digital logic design and computer architecture. Craft novel and creative solutions for verifying complex design micro-architectures. Develop and implement re-usable and optimized formal models and verification code base. Architect correct-by-construction design methodologies for improved formal verification efficiency and productivity. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $207,673 - $277,600/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or related field, and 2 years of experience in the job offered or related occupation.

2 years of experience in each of the following skills is required:

Utilizing design verification techniques, tools, and methodologies to verify and improve chip design and architecture.

Designing and implementing a verification environment using Verilog and System Verilog.

Experience architecting correct-by-construction design methodologies for improved verification efficiency.

Utilizing scripting language skills to develop and maintain verification infrastructure.

Leveraging programming language skills such as C and C++ to verify complex data path designs.

Utilizing Design verification skills to run regressions, including experience in root cause failing designs, bug tracking, and analyzing coverage.

Utilizing SoC design and verification knowledge to drive and maintain deliverables and support cross-functional engineering.

Leveraging design knowledge to drive design teams and improve SoC architecture.

Utilizing RTL debugging and digital system design to achieve the performance and functional goals of the design.

Preferred Qualifications

N/A