Graphics FE Implementation Engineer
Confirmed on the employer's own hiring board on Nov 15, 2026. First seen by Alion on Nov 10, 2025. Apple scores A on the Alion truth index.
Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, resourceful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.
Description
Candidates will be responsible for PPA optimization of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Minimum Qualifications
Experience with physical synthesis, including logic and PPA optimization techniques
Experience with Verilog, System Verilog or other scripting languages
Experience using logic equivalence tools for RTL and Gate-level designs
BS + 3 years of relevant experience
Preferred Qualifications
Understanding and application of physical design (PD) and static timing analysis (STA) principles
Ability to analyze critical paths and guide RTL designs to optimal solutions
Collaborate effectively with IP teams spanning multiple sites
Familiarity with DFT insertion
Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level
Experience implementing ECOs for functionality and timing