Analog & RF IC Senior Layout Engineer

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Job Description:

The Opportunity

Join an industry-leading team of innovators to build the next generation of high-tech hardware. As an Analog/RF Layout Engineer, you won’t just watch from the sidelines-you'll be in the trenches of custom IP block design, translating complex schematics into physical reality on the world’s most advanced process nodes.

The Mission

We are looking for a high-energy engineer to support our circuit design teams in creating world-class silicon. If you’re obsessed with the intersection of physics and circuit design, this role offers a front-row seat to the full silicon design cycle.

What You’ll Do

• Bridge the Gap: Translate circuit schematics into DRC/LVS-clean layouts for critical IP blocks.

• Collaborate & Strategize: Partner with senior designers on floorplanning, power/ground architecture, and precision device matching.

• Master the Tools: Leverage industry-standard EDA tools and cutting-edge technology nodes (FinFET and beyond).

• Impact the Roadmap: Participate in schedule assessments and top-level integration for projects that define our products' success.

The Experience You’ll Gain

• Full-Cycle Layout: Take ownership of custom top-level and IP blocks from initial floorplanning to final tape-out and sign-off.

• Precision Engineering: Master the art of routing critical nets and matching devices to ensure peak performance in high-frequency environments.

• Advanced Nodes: Navigate the nuances of layout on the industry’s most advanced technology nodes, where every nanometer counts.

Knowledge & Experience

• Circuit Expertise: Extensive experience with the layout of high-speed custom analog and digital circuits (e.g., TX, RX, SerDes, and PLLs).

• Tool Proficiency: Deep familiarity with the Cadence Virtuoso tool suite for designing and verifying high-speed custom circuits, including the Virtuoso VXL layout suite and Mentor Calibre verification.

• Advanced Nodes: Proven design and layout experience in advanced FinFET nodes is required.

• Problem Solving: A wide-ranging track record demonstrating both a thorough understanding of layout fundamentals and the creativity needed to solve complex circuit layout challenges.

Education & Qualifications

• Preferred: A BS degree in Electrical Engineering (or a related field) with 8+ years of related experience, OR an MS degree in Electrical Engineering (or a related field) with6+ years of related experience.

Why Join Us?

• True Collaboration: Work side-by-side with some of the industry's most creative and brilliant designers.

• Pure Innovation: Solve real-world physics and parasitic challenges on "bleeding-edge" silicon.

• Future-Proof Career: Build a highly sought-after skill set in analog/mixed signal layout that is vital for the future of Wireless, wireline, and AI hardware.

Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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