Senior Design Lead

HCLTech • IT Consulting & Digital Transformation • IT Outsourcing & Dedicated Teams • Python • Perl • 2 days ago

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Salary

≈ $24k – $55k per year (Estimated)

Location

In office (India)

Seniority

Staff · 7+ years exp

Confirmed on the employer's own hiring board on Oct 24, 2026. First seen by Alion on Oct 23, 2026.

Overview

Company

Impact

Profile match

HCLTech

HCLTech is a major Indian multinational information technology (IT) services and consulting company headquartered in Noida, Uttar Pradesh. Spun off from the original HCL Group in 1991, it ranks as one of India's largest technology companies alongside firms like TCS, Infosys, and Wipro.

hcltech.com • HQ: Noida, India • Science & Engineering • Professional Services • Cybersecurity • Systems Integrators • IT Consulting & Digital Transformation • IT Outsourcing & Dedicated Teams • 5000+ employees • Est. 1976

Tech stack of HCLTech

Job Summary

7 - 10 years of relevant industry experience in Analog/Mixed-Signal Layout Design.
Experience in one or more of the following domains:
- Power Management
- Data Converters
- High-Speed Analog
- IO Layout
- Clocking Solutions
- Custom IP Development.

Key Responsibilities

Design high-quality, schematic-driven physical layouts for analog, mixed-signal, and custom digital blocks (e.g., PLLs, ADCs, DACs, LDOs, and PHY IPs).
Lead a team senior/junior layout design engineer, ensuring delivery excellence.
Drive execution and debugging of DRC, LVS, ERC, Antenna, and EMIR checks to ensure silicon-proven compliance.
Lead layout reviews, estimate schedules, and delegate sub-block tasks. Mentor junior/mid-level layout engineers and enforce design best practices.
Work closely with circuit designers, DFM (Design for Manufacturing) experts, and global engineering teams to optimize Power, Performance, and Area (PPA).
Evaluate new EDA tools, develop automation scripts (Skill/Perl/Python), and optimize layout methodologies to improve overall productivity.

Skill Requirements

Hands-on experience in one or more of the following technologies is preferred:

Intel Advanced Nodes
TSMC N16 / N7 / N5 / N3
Samsung Advanced Process Nodes
Global Foundries Technologies
Any BCD or Bi-CMOS process nodes.

Other Requirements

Layout Editor: Cadence Virtuoso / Synopsys Custom Compiler
Physical Verifications: Calibre / PVS / Assura / ICV
Reliability:
- EM-IR: Voltus / Totem / mPower
- ESD: PERC

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