Technical Architect

Job Summary

A GPIO (General-Purpose Input/Output) Circuit Design Engineer is responsible for designing, optimizing, and verifying the custom mixed-signal and digital I/O structures that bridge an integrated circuit (IC) or System-on-Chip (SoC) core logic with the outside world. This role involves transistor-level design, electrostatic discharge (ESD) protection integration, and power-performance-area (PPA) optimization on advanced process nodes.

Job Summary

• Department: Technology Foundation / IO team
• Experience Level: Mid to Senior Level (typically 7+ years in semiconductor IP design)
• Core Focus: Transistor-level design of I/O buffers, level shifters, receivers, and reliability circuits.

Key Responsibilities

Key Responsibilities

1. Circuit Design & Optimization

• Design and optimize standard and specialized GPIO circuits (including push-pull/open-drain output buffers, Schmitt triggers, level shifters, and programmable pull-up/pull-down resistors).
• Ensure proper voltage domain transitions using level-up and level-down shifters between low-voltage core logic (e.g., 0.8V) and higher-voltage I/O rings (e.g., 1.8V or 3.3V).
• Manage multi-voltage signaling architectures and high-impedance (Hi-Z) tri-state buffer controls.

2. Simulation & Verification

• Perform transistor-level circuit simulations (HSPICE/Spectre) to analyze performance, leakage, and robustness across process, voltage, and temperature (PVT) corners.
• Run static and dynamic reliability checks, including electromigration (EM), IR drop, and electrical overstress (EOS).

3. Layout, ESD & Reliability Integration

• Collaborate closely with layout engineers to ensure matching, parasitic minimization, and strict Design Rule Checking (DRC) / Layout Versus Schematic (LVS) compliance.
• Co-design and verify Electrostatic Discharge (ESD) and latch-up protection structures to guarantee foundry reliability standards.

4. Cross-Functional Collaboration

• Interface with SoC integration, RTL design, and digital verification teams to support pad ring assembly and core-to-I/O boundary timing closure.
• Participate in silicon bring-up, lab debugging, and model-to-silicon validation correlation.

Skill Requirements

• Technical Domain: Strong fundamentals in CMOS mixed-signal circuit design and deep sub-micron device physics.
• EDA Tools: Proficiency with industry-standard IC design tools such as Cadence Virtuoso, Synopsys HSPICE, or Siemens EDA (Mentor Graphics) platforms.
• Languages & Scripting: Familiarity with hardware description languages (Verilog/VHDL) and scripting languages (Python, Tcl, Perl) to automate design flows.
• Standards & Protocols: Knowledge of JEDEC standards, GPIO control registers, and bus interfaces (like AMBA APB) is highly preferred

Other Requirements

• Education: Bachelor’s or Master’s degree in Electronics/Electrical Engineering or a related technical discipline.