Technical Architect

Job Summary

We are seeking highly motivated Senior Memory Architect who can architect, design, develop, and optimize memory IPs (SRAM, ROM, Register files, etc.) for advanced semiconductor nodes.

Key Responsibilities

Key Responsibilities

• To architect memory compiler and custom memory instance design
• To analyze memory specs and meet PPA requirement for given compiler design
• Perform transistor-level design and simulations (HSPICE, Spectre).
• Conduct corner analysis, Monte Carlo simulations and variation aware design.
• Debug design issues across PVT conditions.
• Identify design margin measurements and create simulation setups and perform simulations
• To create setups for Bitcell Analysis, Sense amp analysis and self-time analysis and perform these verifications
• To create critical path schematic and simulations setup. Perform simulations and debug.
• To design and optimize all kinds of leaf cells in memory from scratch
• To integrate all the leaf cells into memory instance and perform top level simulations
• To manage multiple projects and guide team towards project closure
• Collaboration with layout and Verilog modelling team

Skill Requirements

• Good understanding of different Memory architectures (SRAM, ROM, emerging memory is a plus)
• Familiar with bitcell and peripheral design
• Strong understanding of CMOS fundamentals
• Good understanding of Low-power design techniques
• Good understanding of various Read and Write assist circuits design techniques
• Good understanding of Redundancy and memory BIST feature
• Good Experience with Fast Spice and True Spice simulators
• Good understanding of critical path schematic creation for memory compiler modelling
• Good understanding of timing and power arcs required for memory characterization
• Good understanding of layout dependent effects in design
• Good understanding of parasitic extraction tool working and options associated with it

Other Requirements

• Knowledge of memory compilers or embedded memory IP development
• Knowledge of FinFET technologies
• Exposure to ESPCV tool working