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Design Engineer II

Cadence Design Systems • EDA Software • Semiconductor IP & Chip Design Services • Python • C++ • SystemVerilog • Perl • 9 days ago
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Salary
≈ $19k – $44k per year (Estimated)
Location
In office (Noida)
Seniority
Middle
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 10, 2026. First seen by Alion on Oct 1, 2026. Cadence Design Systems scores B on the Alion truth index.

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Company
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Profile match

Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
cadence.com • HQ: San Jose, United States • Semiconductor IP & Chip Design Services • EDA Software • 5000+ employees • Est. 1988
Tech stack of Cadence Design Systems

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Overview:

Key Responsibilities:

  • Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
  • Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis.
  • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Required Qualifications:

  • B.Tech/M.Tech in ECE with
  • Experience in SystemVerilog/UVM and C/C++ for architectural modeling.
  • Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
  • Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
  • Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.

We’re doing work that matters. Help us solve what others can’t.

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