Lead Design Engineer

Cadence Design Systems • SystemVerilog • Verilog • 2 years ago
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Salary
≈ $27k – $73k per year (Estimated)
Location
In office (Noida)
Seniority
Staff · 4+ years exp
Employment
Full-Time
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Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
cadence.com • HQ: San Jose, United States • Hardware • Simulation & Digital Twin • EDA • Semiconductors • Software • 5000+ employees • Est. 1988

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.

  • 4+ years of Design Verification experience with SV/UVM
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • Design Verification experience verifying complex designs and leading projects from concept to verification closure.
  • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
  • Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.

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