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Sr Principal Design Engineer

Cadence Design Systems · EDA Software · Semiconductor IP & Chip Design Services · Bachelor's Degree · Verilog · Perl · TCL Scripting · 1 year ago
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Salary
≈ $31k – $71k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Principal · 12+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 31, 2026. First seen by Alion on Sep 1, 2025. Cadence Design Systems scores B on the Alion truth index.

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Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
cadence.com · HQ: San Jose, United States · Semiconductor IP & Chip Design Services · EDA Software · 5000+ employees · Est. 1988
Tech stack of Cadence Design Systems
Backed by Sequoia Capital

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently

Should be good in Perl/Tcl scripting and automation

We’re doing work that matters. Help us solve what others can’t.

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