Senior Engineer, ASIC Digital Design (System IP Verification)

About GF

GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power-efficient and high-performance solutions for high-growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted and holistic technology partner for customers around the world. GF’s talented global team remains focused every day on security, longevity and sustainability. For more information, visit www.gf.com.

Introduction

Join the System IP Verification team in Hsinchu to verify configurable system-level IP and subsystems for next-generation RISC-V processor platforms, including coherent memory subsystems, interconnect, low-power and SoC infrastructure IP.

You will work with experienced engineers and receive technical mentoring while developing practical skills in verification planning, SystemVerilog/UVM, simulation, regression, coverage, automation and debug. You will collaborate with global architecture, RTL design, modeling, formal verification, software and system validation teams.

Responsibilities

• Learn the architecture and intended behavior of System IP blocks and subsystems, contribute to specification reviews and verification planning, and take increasing ownership of identifying and verifying functional, stress and corner-case scenarios.
• Develop and maintain verification content using SystemVerilog/UVM or related methodologies, including tests, sequences, monitors, scoreboards, reference models, assertions, checkers and functional coverage, with mentoring from experienced engineers.
• Run simulation and regression environments; analyze logs, waveforms and coverage results; isolate issues across RTL, testbench, protocol, configuration, clock/reset and subsystem-interaction boundaries; document findings and collaborate on root-cause analysis.
• Apply Python, C/C++ or shell scripting to improve test generation, verification automation, regression analysis, data analysis and debug productivity.

• Collaborate with architecture,RTL design, formal verification, modeling, software, infrastructure and processor/subsystem verification teams to improve product quality and contribute to agreed quality and project milestone objectives.

• Document verification intent, implementation, results and lessons learned, and actively participate in technical reviews, team knowledge sharing and continuous improvement.

Required Qualifications

• Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or a closely related field.
• Strong academic foundation indigital logic, digital IC design, computer architecture, VLSI, embedded systems or a related area.
• Hands-on programming or hardware-description experience in at least one of the following: Verilog/SystemVerilog, C/C++ or Python
• Basic understanding of RTL design, simulation and debugging concepts, with the ability to analyze technical problems systematically.
• Ability to learn unfamiliar concepts and clearly communicate technical assumptions, findings and open questions in written and spoken English.
• Ability to work constructively with engineers across functions and geographical locations.

Preferred Qualifications

• Thesis, research, internship or project experience involving computer or processor architecture, RISC-V, cache or memory systems, interconnect/NoC, SoC integration, FPGA or digital verification.
• Exposure to SystemVerilog/UVM, constrained-random verification, assertions/SVA, functional or code coverage, formal verification, performance modeling or processor/subsystem-level validation.
• Familiarity with Linux, Git and EDA simulation or debug tools such as VCS/Verdi, Xcelium/SimVision, Questa, Verilator or equivalent tools.
• Experience applying Python, C/C++ or shell scripting to verification automation, test
• Interest in developing deeper expertise in cache coherency, memory ordering, interconnect protocols, low-power verification, functional safety/security or verification automation.

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