Package Design Engineer
Confirmed on the employer's own hiring board on Nov 8, 2026. First seen by Alion on Nov 5, 2026. Google scores B on the Alion truth index.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI, Thermal/Mechanical, Assembly, and PCB engineers to create complex, high-performance substrate designs, where your goal is to optimize package substrate design for electrical performance, reliability, and assembly.
You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, which contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Develop physical package substrate design of large form-factor package for ML high-performance computers (HPCs).
- Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity.
- Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
- Collaborate closely with signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
- Define and document the requirements for the package substrate design and bill of materials (BOM).
Qualifications
Minimum qualifications:
- Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
- 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
- Experience in chip package substrate layout, design verification, DFM and taping out for production.
- Experience in design automation and scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience in working with cross-functional teams including chip design, SI/PI, and PCB design teams.
- Experience in 2.5D/3.5D advanced package design.
- Experience in physical verification flow (LVS, DRC, connectivity).
- Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD).
- Ability to write scripts to customize elements of the Cadence or Mentor workflow.