Senior Technical Lead - Post Silicon Validation

Job Summary

We are looking for a Silicon Interposer Design Engineer to drive the physical design, layout, and technology development of silicon interposers used in next-generation 2.5D and 3D heterogeneous integration platforms. You will own the interposer design from architecture definition through tapeout, working at the intersection of semiconductor process technology, package integration, and system-level performance optimization.

Key Responsibilities

Lead the physical design and layout of silicon interposers for multi-chiplet integration (compute, HBM, I/O, networking dies)

• Define interposer architecture including die placement, bump map assignment, RDL routing strategy, TSV farm layout, and power/ground distribution
• Develop and optimize RDL (Redistribution Layer) routing for high-density die-to-die interconnects, ensuring compliance with electrical, thermal, and mechanical constraints
• Design TSV (Through-Silicon Via) arrays and transitions - including TSV placement, keep-out zones, stress-aware floorplanning, and landing pad optimization
• Collaborate with SI/PI engineers to meet signal integrity and power delivery targets across the interposer
• Define and validate interposer stackup (metal layers, dielectric thickness, TSV dimensions) in coordination with foundry process capabilities
• Perform DRC/LVS verification and ensure design compliance with foundry design rules (TSMC CoWoS, UMC, GlobalFoundries, etc.)
• Work with EDA tool flows for interposer-specific design (custom routing, via pillar arrays, micro-bump pitch optimization)
• Co-optimize interposer design with package substrate and PCB teams for seamless chip-package-board integration
• Support thermal-mechanical analysis by providing accurate layout data for warpage, stress, and reliability simulations
• Interface with foundry partners for technology selection, design rule clarification, and tapeout execution
• Drive DFM/DFT strategies to improve yield and testability of interposer-based products
• Support silicon bring-up, debug, and failure analysis of interposer-related issues

Skill Requirements

5+ years of experience in silicon interposer design, advanced packaging physical design, or semiconductor back-end-of-line (BEOL) design

• Strong proficiency with physical design and layout tools:
• Layout & Routing: Cadence Virtuoso, Cadence APD (Advanced Package Designer), Synopsys IC Compiler II, Siemens Calibre
• Verification: Cadence PVS, Mentor Calibre (DRC/LVS/ERC)
• Parasitic Extraction: StarRC, QRC, Calibre xRC
• Deep understanding of silicon interposer process technology:
• RDL metallization (Cu damascene, semi-additive process)
• TSV fabrication (via-first, via-middle, via-last)
• Micro-bump and C4 bump technology
• Wafer thinning and backside processing
• Experience with high-density routing at fine pitch (< 1 µm L/S for RDL, < 10 µm TSV pitch)
• Knowledge of design-for-reliability (DFR): electromigration, stress migration, thermal cycling, and Cu pumping in TSVs
• Familiarity with foundry PDKs and process design kits for interposer technologies
• Scripting skills (Python, Tcl, SKILL) for design automation and custom DRC rule development

Other Requirements

Technical Environment Domain Tools & Technologies Physical Design & Layout Cadence Virtuoso, APD, Allegro SiP, Synopsys IC Compiler II Verification (DRC/LVS) Parasitic Extraction EM/Electrical Analysis Thermo-Mechanical Scripting & Automation Foundry Platforms Interconnect Standards Cadence PVS, Siemens Calibre, IC Validator StarRC, QRC, Calibre xRC Ansys HFSS, Cadence Clarity, Sigrity Ansys Mechanical, Ansys Icepak, COMSOL Multiphysics Python, Tcl, Cadence SKILL, Perl TSMC CoWoS (S/R/L), UMC, GlobalFoundries, Samsung I-Cube UCIe, HBM3/3E PHY, PCIe Gen5/6, high-speed SerDes

Preferred Qualifications

• Direct experience with TSMC CoWoS (CoWoS-S, CoWoS-R, CoWoS-L), Intel EMIB, or similar 2.5D interposer platforms
• Experience designing interposers for HBM integration (HBM2E/HBM3/HBM3E PHY-to-interposer routing)
• Knowledge of hybrid bonding and direct Cu-Cu interconnect technology for next-generation interposers
• Familiarity with chiplet standards (UCIe, BoW) and their physical implementation on interposers
• Experience with organic interposer or glass-core interposer alternatives
• Understanding of thermo-mechanical simulation tools (Ansys Mechanical, COMSOL) for warpage and stress analysis
• Exposure to photonics integration on silicon interposers (co-packaged optics)
• Track record of successful tapeouts with major foundries
• Publications or patents in advanced packaging or interposer technology