Technical Architect
Confirmed on the employer's own hiring board on Oct 14, 2026. First seen by Alion on Oct 14, 2026.
Job Summary
Standard Cell Characterization Architect/Manager to Lead a project and work on library characterization and model generation for advanced CMOS/FinFET technologies. The role involves generating high-quality Liberty (.lib) files, collaborating with design and layout teams, and supporting automation and validation of characterization flows.
Key Responsibilities
Provide technical leadership to a project and be responsible for overall delivery.
Perform standard cell library characterization and generate:
Timing, power, noise, and variation models
Accurate Liberty (.lib) files
Develop understanding and support for:
Circuit design and layout interactions
View generation and automation flows
Execute SPICE simulations and analyze characterization results
Generate extracted netlists from layout and perform characterization
Validate libraries through QA checks and consistency verification
Work with different collateral views:
GDS, .lib, Verilog (.v), IBIS (.ibs), .db, etc.
Collaborate with design, layout, and CAD teams for end-to-end delivery
Required Skills (Must-Have)
Should be able to provide Technical Leadership for a project.
Should be able to setup flow from scratch and mentor team members
Strong understanding of CMOS and FinFET device characteristics
Strong knowledge of digital circuit design (combinational & sequential)
Strong understanding of SPICE simulation
Strong knowledge of .lib generation and characterization flow
Strong understanding of library characterization concepts, including:
Timing, noise, power, and variation models
Solid knowledge of:
NLDM (Non-Linear Delay Model)
CCS (Composite Current Source Model)
LVF models
Strong understanding of collateral views (GDS, .lib, Verilog, IBIS, .db)
Strong understanding of:
Library validation and quality checks (QA)
Strong proficiency in scripting:
Linux, Perl, Python, Tcl
Desired Skills (Good-to-Have)
Must be able to lead a project and team
Must be able to setup flow from scratch
Strong understanding of project and flow understanding
Knowledge of deep submicron process challenges
Hands-on experience in advanced nodes (≤16nm, FinFET)
Good communication and teamwork skills
Positive learning attitude and adaptability
Education & Experience
B.Tech / M.Tech in Electronics / VLSI / related field with 12-15 years of experience in Standard cell characterization / view generation
Keywords
Standard Cell Characterization, Liberty (.lib), SPICE Simulation, CMOS, FinFET, NLDM, CCS, LVF, Timing Models, Power Models, SiliconSmart, Liberate, View Generation, QA Validation
Key Responsibilities
Standard Cell Characterization Architect/Manager to Lead a project and work on library characterization and model generation for advanced CMOS/FinFET technologies. The role involves generating high-quality Liberty (.lib) files, collaborating with design and layout teams, and supporting automation and validation of characterization flows.
Key Responsibilities
Provide technical leadership to a project and be responsible for overall delivery.
Perform standard cell library characterization and generate:
Timing, power, noise, and variation models
Accurate Liberty (.lib) files
Develop understanding and support for:
Circuit design and layout interactions
View generation and automation flows
Execute SPICE simulations and analyze characterization results
Generate extracted netlists from layout and perform characterization
Validate libraries through QA checks and consistency verification
Work with different collateral views:
GDS, .lib, Verilog (.v), IBIS (.ibs), .db, etc.
Collaborate with design, layout, and CAD teams for end-to-end delivery
Required Skills (Must-Have)
Should be able to provide Technical Leadership for a project.
Should be able to setup flow from scratch and mentor team members
Strong understanding of CMOS and FinFET device characteristics
Strong knowledge of digital circuit design (combinational & sequential)
Strong understanding of SPICE simulation
Strong knowledge of .lib generation and characterization flow
Strong understanding of library characterization concepts, including:
Timing, noise, power, and variation models
Solid knowledge of:
NLDM (Non-Linear Delay Model)
CCS (Composite Current Source Model)
LVF models
Strong understanding of collateral views (GDS, .lib, Verilog, IBIS, .db)
Strong understanding of:
Library validation and quality checks (QA)
Strong proficiency in scripting:
Linux, Perl, Python, Tcl
Desired Skills (Good-to-Have)
Must be able to lead a project and team
Must be able to setup flow from scratch
Strong understanding of project and flow understanding
Knowledge of deep submicron process challenges
Hands-on experience in advanced nodes (≤16nm, FinFET)
Good communication and teamwork skills
Positive learning attitude and adaptability
Education & Experience
B.Tech / M.Tech in Electronics / VLSI / related field with 12-15 years of experience in Standard cell characterization / view generation
Keywords
Standard Cell Characterization, Liberty (.lib), SPICE Simulation, CMOS, FinFET, NLDM, CCS, LVF, Timing Models, Power Models, SiliconSmart, Liberate, View Generation, QA Validation
Skill Requirements
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Other Requirements
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