Senior Staff Verification Engineer

Your Role

Key responsibilities in your new role

• Perform and supervise detailed Simulation, verification and validation of integrated circuits.
• Develop testbenches using System Verilog and UVM for functional and power aware RTL
• Develop UVM components like agents (active and passive), scoreboards and environments etc., develop assertions, functional coverage.
• Develop test plans, UVM based test sequences, layered sequences, virtual sequencers
• Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware, and gate level timing simulation.
• Provide regression setup, debug of RTL and gate level netlist.
• Review industry standard spec and augment test plan to improve quality of verification
• Participate in post silicon bring up, validation and compliance testing and debug
• Work collaboratively with cross-functional teams like Product Architect, Designers, Project leads, Project managers
• Subject matter expert level communication with customer (and/or marketing), including presentation in design reviews, representing the verification team on weekly conference calls, defining/tracking/working to ensure schedule adherence, interactive problem solving, and customer communication under pressure, etc.

Your Profile

Qualifications and skills to help you succeed

• Bachelor’s in electrical engineering or equivalent and 8+ years of experience
• Proven expertise with UVM and/or System Verilog based verification
• Excellent understanding of ASIC verification methodologies and proven experience of verification
• Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira.
• Strong written and verbal communication skills and ability to work independently.

#WeAreIn for driving decarbonization and digitalization.

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