Senior Staff Device Engineer

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

We are seeking a Senior Staff Device Engineer with broad technical expertise spanning semiconductor technology, device physics, circuit analysis, CAD tools, and yield engineering. This role focuses on diagnosing product yield and failure issues from the circuit level down to the transistor and fab process level, driving root cause analysis and corrective actions, and optimizing process conditions for robust yield, reliability, and NPI success. The engineer will collaborate closely with Design, Layout, Product Engineering, and Foundries, and will advise Design and Layout teams on design changes that improve yield and reliability.

Responsibilities

1. Device Engineering & Circuit Analysis

• Analyze circuit failures and yield anomalies, tracing and isolating failure behavior to the transistor level or specific fab process steps using CAD navigation and circuit/layout knowledge.

• Study Process Design Rules, DRC, DFM guidelines, device construction, transistor characteristics, and SPICE model corner coverage to proactively identify structural or layout-dependent weak points.

• Perform transistor characterization by designing test keys (SLM, test chip design) for advanced transistor characterization and monitoring of reliability limits.

• Modify Design Rule Checks (DRC) or collaborate with CAD teams to screen specific wafer lots for weak layout features susceptible to process drift.

• Work closely with Product Engineers to refine or modify test scripts when narrowing down failure root causes.

2. Yield Engineering & Sustaining

• Own sustaining activities including yield improvement, process window optimization, and SPC monitoring on production silicon.

• Analyze WAT, inline, and final test data to identify process drift, yield loss mechanisms, and reliability risks; drive root cause and corrective action with foundry process owners.

• Correlate complex electrical failure data (sort, bitmap, and customer returns) with WAT data to pinpoint process shifts.

• Perform product process corner and design window studies to optimize process targets.

• Collaborate with Design, Product Test, and Failure Analysis teams to debug and root cause systematic yield issues.

3. Failure Analysis & Fault Isolation

• Support fault isolation by translating complex electrical test failures (sort, bitmap, customer returns) into precise layout-level regions for localized de-layering, nanoprobing, SEM, and TEM analysis.

• Perform product failure diagnosis for yield debug and failure localization, including bitmap analysis.

• Analyze structural PFA cross-sections, material anomalies, and physical defects alongside transistor characterization data to identify fab-side or layout-dependent root causes.

• Coordinate failure analysis efforts across internal teams and foundry FA resources.

4. Quality & Customer Suppor t

• Support customer-facing quality escalations including 8D and CAR responses.

Requirements

• M.S. or Ph.D. in Electrical Engineering, Microelectronics, Materials Science, or a related field, with 10+ years of relevant experience in a fabless semiconductor or foundry ecosystem.

• Device Physics & Reliability: Strong knowledge and hands-on experience in transistor-level characterization, compact modeling, and semiconductor reliability mechanisms (e.g., HCI, NBTI, TDDB).

• Circuit & Layout CAD: Full proficiency in industry-standard CAD tools (e.g., Cadence Virtuoso, Synopsys) for schematic capture, layout verification (DRC/LVS), and physical design analysis.

• Design for Manufacturing (DFM): Proven ability to identify physical weak points in product layouts and directly link them to specific fab manufacturing constraints.

• Demonstrated experience with WAT parametric analysis, yield engineering, SPC, failure diagnosis and analysis coordination, and process window optimization.

• Understanding of semiconductor product test flow and ability to engage effectively with manufacturing test and product engineering teams.

• Familiarity with Lattice FPGA architecture or programmable logic products a plus.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.