Packaging Architect

The ideal candidate will play a key role in identifying the optimal package architecture and key packaging technologies, establishing 3rd party relationships, communicating with partners and addressing challenges in areas such as 2.5D/3D/3.5D and System technology

optimization with advanced Si nodes, including but not limited to CoWoS-S/R/L, EMIB/EMIB-T, SoIC, HBM, FCBGA, and HBPOP. The candidate should demonstrate ownership, high standards, strategic thinking, and customer obsession.

Roles and Responsibilities:

• Identify the optimal package architecture by balancing electrical, thermal, and mechanical performance, meeting project’s timeline.
• Working closely with internal and external partners on silicon-disaggregation and other chiplet strategies for advanced packages, including emerging-memory chiplet integration
• Perform a trade-off analysis across silicon layout, die-to-die connectivity options, and package design/technology, evaluating their impact on key product metrics, including performance, cost, manufacturability, power efficiency, and form factor.
• Identifying critical elements for packaging roadmap, Partner with supply chain engineering experts to define packaging technology and material requirements for substrate fabrication, assembly, and raw material vendors.
• Stay informed about emerging packaging architectures by engaging with the product team and customers in the data center and high-end compute segments.
• Continuously monitor the competitive landscape in packaging technologies and solutions.