Confirmed on the employer's own hiring board on Sep 24, 2026. First seen by Alion on Jun 10, 2026.
About the Role:
Power integrity is becoming a first-order design constraint at advanced technology nodes. As a Senior Power Integrity (PI) Analysis Engineer, you will own IR-drop sign-off and power grid implementation for high-performance CPU blocks, bridging physical design and system-level power delivery to ensure robust, silicon-proven voltage margins.
What You’ll Do:
1. Own block-level IR drop sign-off (static and dynamic) and power grid implementation for CPU blocks.
2. Set up PI analysis environments, including package models and bump/ball map configurations.
3. Define power grid requirements in close collaboration with physical design teams.
4. Drive power grid architecture decisions to meet sign-off criteria across all operating points.
5. Deliver CPM models for SoC-level integration and customer power delivery modeling.
6. Develop, document, and champion advanced PI methodologies through MediaTek’s worldwide PI forum.
7. Collaborate with package, board, and PMIC teams to ensure end-to-end power delivery integrity.
Location: San Jose, CA/Austin, TX

