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Salary
≈ $90k – $170k per year (Estimated)
Location
In office (Austin)
Seniority
Senior

Confirmed on the employer's own hiring board on Sep 24, 2026. First seen by Alion on Jun 10, 2026.

Overview
Company
Impact
Profile match
MediaTek Inc. is a global fabless semiconductor company specializing in system-on-chip (SoC) architectures and digital multimedia processing technologies. The enterprise designs and markets integrated circuits for smartphones, smart home devices, IoT hardware, wireless connectivity solutions, automotive electronics, and custom AI chips for edge and cloud applications. Headquartered in Hsinchu, Taiwan, the organization operates an international network of research, development, and sales offices serving original equipment manufacturers (OEMs) and technology brands worldwide.
MediaTek is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading-edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, MediaTek drives advancements in transformative technologies such as AI, 5G/6G, and Wi-Fi 8. Our high-performance, power-efficient solutions form the foundation for a smarter, more connected world, enabling devices from smartphones, smart homes, and AI PCs to high-performance computing, automotive, and AI data centers. As a trusted partner to the world's leading brands, we are committed to ensuring access to world-class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity.

About the Role:

Power integrity is becoming a first-order design constraint at advanced technology nodes. As a Senior Power Integrity (PI) Analysis Engineer, you will own IR-drop sign-off and power grid implementation for high-performance CPU blocks, bridging physical design and system-level power delivery to ensure robust, silicon-proven voltage margins.

What You’ll Do:

1. Own block-level IR drop sign-off (static and dynamic) and power grid implementation for CPU blocks.

2. Set up PI analysis environments, including package models and bump/ball map configurations.

3. Define power grid requirements in close collaboration with physical design teams.

4. Drive power grid architecture decisions to meet sign-off criteria across all operating points.

5. Deliver CPM models for SoC-level integration and customer power delivery modeling.

6. Develop, document, and champion advanced PI methodologies through MediaTek’s worldwide PI forum.

7. Collaborate with package, board, and PMIC teams to ensure end-to-end power delivery integrity.

Location: San Jose, CA/Austin, TX

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