Senior STA Engineer

MediaTek is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading-edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, MediaTek drives advancements in transformative technologies such as AI, 5G/6G, and Wi-Fi 8. Our high-performance, power-efficient solutions form the foundation for a smarter, more connected world, enabling devices from smartphones, smart homes, and AI PCs to high-performance computing, automotive, and AI data centers. As a trusted partner to the world's leading brands, we are committed to ensuring access to world-class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity.

ABOUT THE ROLE

Mobile CPUs push timing sign-off to its limits - ultra-wide voltage ranges, aggressive multi-OPP targets, and sub-2nm parasitics demand creative margin methodology. As a Senior STA Engineer you will be the timing authority for one or more CPU blocks, partnering with PD, RTL, and DFT teams to deliver clean sign-off on MediaTek's next-generation SoCs.

WHAT YOU'LL DO

• Own block-level STA sign-off: constraint development, multi-scenario regression, and timing closure
• Generate and drive timing and power ECOs through to resolution
• Partner with RTL and DFT teams to define accurate functional and test-mode constraints
• Develop and champion advanced margining methodologies (AOCV/POCV) calibrated to silicon
• Analyze clock tree quality; guide physical implementation toward scalable, convergence-friendly CTS
• Build custom sign-off recipes for power recovery and timing closure in Tempus/PrimeTime
• Deliver timing models (ETM, Hyperscale) and SDC/timing budgets for SoC integration
• Participate in MediaTek's worldwide STA forum; help define next-generation margin methodologies