Confirmed on the employer's own hiring board on Sep 24, 2026. First seen by Alion on Jul 20, 2026.
About the Role
We are seeking a Senior Physical Design Engineer to drive Advanced Place & Route (APR) and physical verification (PV) signoff for high-performance CPU cores in 3nm and other leading-edge technology nodes. In this role, you will own critical implementation stages-from early PPA evaluation and risk assessment to advanced clock tree design and signoff-helping us deliver highly optimized, silicon-proven CPU solutions.
Key Responsibilities
Perform APR implementation and PV signoff for high-performance CPU designs in 3nm and other advanced technology nodes.
Develop and optimize advanced clock tree structures to meet stringent performance, power, and skew/jitter targets.
Conduct early-stage PPA evaluation and risk assessment to guide architectural and implementation decisions.
Collaborate with front-end design, STA, IR/EM, and verification teams to close timing, power, and physical design issues.
Support and enhance design methodologies and flows to improve quality, scalability, and turnaround time.

