ASIC Engineer, Infrastructure Silicon Validation

Meta's Infrastructure Silicon team designs and deploys custom silicon solutions that power the compute, networking, and storage infrastructure underpinning Meta's global data centers. As a principal-level ASIC engineer focused on infrastructure silicon validation, you will define and drive the end-to-end validation strategy for custom ASICs spanning compute accelerators, network ASICs, and storage controllers. In this role, you will shape the technical direction of silicon bring-up, functional validation, and post-silicon debug methodologies, ensuring that Meta's custom silicon programs meet the reliability and performance demands of hyperscale infrastructure deployments.

Responsibilities

Define and own the long-term post-silicon validation strategy for custom infrastructure ASICs, including compute accelerators, network ASICs, and storage controllers across multiple program generations Architect scalable validation frameworks and test methodologies for functional verification, performance characterization, and reliability qualification of custom silicon in data center environments Lead silicon bring-up activities including power-on sequencing, clock and reset validation, memory interface bring-up, and high-speed SerDes link characterization Drive root-cause analysis and debug of complex silicon failures using lab instrumentation, logic analyzers, oscilloscopes, and custom diagnostic firmware Collaborate with pre-silicon design and verification teams to ensure testability requirements, DFT coverage, and scan chain integrity are incorporated early in the design cycle Partner with system software, firmware, and platform engineering teams to co-develop validation infrastructure, diagnostic tools, and automated test suites for silicon characterization Establish silicon validation milestones, risk assessments, and readiness criteria for tape-out, first silicon, and production qualification gates across multiple concurrent programs Influence silicon architecture and design decisions by providing post-silicon feedback loops that inform future ASIC generations and improve first-pass silicon success rates Mentor other engineers across the validation organization and drive adoption of best practices in post-silicon debug, test automation, and characterization methodology Represent the silicon validation organization in cross-functional technical reviews, executive program readiness discussions, and external partner engagements with foundry and IP vendors

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 15+ years of experience in post-silicon validation, silicon bring-up, or ASIC characterization for high-complexity custom ASICs in compute, networking, or storage domains Experience defining and executing validation strategies for high-speed interfaces including PCIe, DDR, HBM, Ethernet, or custom SerDes links at multi-gigabit data rates Experience with DFT methodologies including scan, BIST, JTAG, and boundary scan as applied to post-silicon debug and production test coverage Experience leading multi-generational silicon validation programs from tape-out through production qualification in a hyperscale or high-volume manufacturing environment Experience developing automated silicon characterization and regression frameworks using scripting languages such as Python, Tcl, or equivalent Background in developing silicon validation IP or reusable test infrastructure that spans multiple ASIC programs or product families Experience collaborating with foundry partners on process-related failure analysis, yield improvement, and reliability qualification for advanced process nodes Familiarity with formal verification, emulation platforms, or pre-silicon simulation environments and their correlation to post-silicon validation outcomes Experience validating custom silicon deployed in large-scale data center infrastructure, including thermal, power integrity, and signal integrity characterization under production workloads