Lead Engineer - DFT
Confirmed on the employer's own hiring board on Sep 26, 2026. First seen by Alion on Jun 19, 2026.
Job Description:
1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..)
2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR)
3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test
4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system
5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors
6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction
- Proven track record of delivering results and meeting quality, cost, and time-to-market objectives
7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization
8. Stakeholder influencing and people skills must be excellent.
9. Needs to be able to set aggressive goals and manage risks effectively
10. Must have a thorough understanding of tool development methodology.
11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements.
12. MS or Ph.D. Engineering degree (EE or equivalent) with 4-7 years semiconductor industry experience.