Senior RTL Design Engineer - ASIC/SoC
First seen by Alion on Oct 1, 2026.
Senior RTL Design Engineer / Lead
About the Role :
We are seeking an experienced Senior RTL Design Engineer / Lead to drive RTL development and integration for complex ASIC/SoC projects. The role requires strong hands-on expertise in RTL architecture, ARM-based SoCs, AMBA protocols, synthesis, timing analysis, and design quality, along with the ability to independently own design blocks and subsystems.
Key Responsibilities :
- Own RTL design and implementation for complex IP blocks, subsystems, and SoC components.
- Translate architectural and micro-architectural specifications into efficient, synthesizable RTL.
- Design and integrate ARM core-based SoC components and associated interfaces.
- Drive implementation using AMBA AXI, AHB, and APB protocols.
- Review RTL for functionality, performance, area, power, and coding quality.
- Lead Lint and CDC analysis, identify violations, and drive closure.
- Perform and review ASIC synthesis and Static Timing Analysis (STA).
- Analyze timing issues and work with relevant teams on design optimization and closure.
- Perform formal/equivalency checking to ensure consistency between RTL and implementation stages.
- Support FPGA prototyping and FPGA-based development where applicable.
- Lead RTL debugging and resolve complex integration issues.
- Collaborate with verification, architecture, physical design, firmware, and system teams.
- Participate in design reviews, code reviews, technical planning, and project estimation.
- Mentor junior RTL engineers and establish coding and design best practices.
- Drive assigned deliverables and contribute to project-level technical milestones.
Required Skills :
- 9 - 14 years of experience in RTL Design / ASIC / SoC Design.
- Strong expertise in Verilog/VHDL and synthesizable RTL coding.
- Strong understanding of ARM SoC architecture and integration.
- Extensive experience with AMBA AXI, AHB, and APB protocols.
- Hands-on experience with Lint, CDC, synthesis, and Static Timing Analysis.
- Experience with equivalency checking/formal equivalence.
- Experience with FPGA design and/or FPGA prototyping.
- Strong understanding of digital design, microarchitecture, and SoC integration.
- Strong debugging and problem-solving capabilities.
- Ability to independently own design blocks/subsystems from specification through implementation.
- Strong communication and cross-functional collaboration skills.
Preferred Skills :
- Experience with complex ARM-based SoCs.
- Experience with high-performance or low-power digital designs.
- Exposure to timing optimization, PPA improvement, and design closure.
- Experience reviewing RTL architecture and mentoring design engineers.
- Familiarity with industry-standard EDA tools and ASIC design flows.
Skills
RTL, Verilog, VHDL, AMBA, ARM, Static Timing Analysis, Synthesis, RTL Design, ASIC