RTL Design Engineer

RTL Design Engineer

Experience : 5 - 8 Years

Location : Bangalore / Kochi / Chennai / Pune

Job Type : Full-time

About the Role :

We are looking for a skilled RTL Design Engineer with hands-on experience in ASIC/SoC design projects. The ideal candidate should have strong expertise in RTL coding, ARM-based SoC architecture, AMBA protocols, synthesis, timing analysis, and design quality checks.

Key Responsibilities :

- Execute RTL design and coding for complex digital designs using Verilog/VHDL.

- Integrate ARM core-based designs into SoCs and ensure seamless interface compatibility.

- Design and integrate interfaces based on AMBA protocols, including AXI, AHB, and APB.

- Perform Lint and CDC analysis and address design issues to ensure robust RTL implementation.

- Work on FPGA-based designs and/or FPGA prototyping for development and validation.

- Participate in ASIC synthesis and Static Timing Analysis (STA) activities.

- Perform equivalency checking between RTL and synthesized/netlist implementations.

- Debug RTL and integration issues and work closely with verification teams to resolve design issues.

- Collaborate with architecture, verification, physical design, and other cross-functional teams.

- Contribute to project milestones, design reviews, and technical discussions.

- Maintain design documentation and coding standards.

Required Skills :

- 5 - 8 years of hands-on experience in RTL Design / ASIC / SoC Design.

- Strong proficiency in Verilog/VHDL and RTL coding methodologies.

- Good understanding of ARM-based SoC architecture.

- Hands-on experience with AMBA AXI, AHB, and APB protocols.

- Experience with Lint and CDC analysis.

- Understanding of ASIC synthesis and Static Timing Analysis.

- Experience with equivalency checking and design quality methodologies.

- Exposure to FPGA design or FPGA prototyping.

- Strong debugging and problem-solving skills.

- Good understanding of digital design concepts and SoC integration.

- Strong communication and cross-functional collaboration skills.

Preferred Skills :

- Experience working on complex IP/block-level RTL design.

- Exposure to ARM processor subsystems and SoC interconnects.

- Experience with synthesis, timing constraints, and design optimization.

- Knowledge of industry-standard RTL design and EDA tools.

Skills

RTL, Verilog, VHDL, ASIC, SoC, ARM, RTL Design, Physical Design