DFT - Senior Engineer

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Job Area:

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

OR

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field.

Description

Minimum of 3+ years experience in the area of ASIC/DFT

-In depth knowledge of DFT concepts

-In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis

-Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations

-Expertise in scripting languages such as perl, shell, etc.

-Experience in simulating test vectors

-Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent, TK, TetraMax)

-Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test is a plus

-Ability to work in an international team, dynamic environment

-Ability to learn and adapt to new tools and methodologies.

-Ability to do multi-tasking & work on several high priority designs in parallel.

-Excellent problem solving skills

-Excellent communication and team work skills and good English is require

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