Senior Physical Design Engineer
Confirmed on the employer's own hiring board on Oct 31, 2026. First seen by Alion on Oct 8, 2026.
Own
the physical design flow from RTL - GDSII for complex blocks/sub-systems.
Drive
floorplanning, power planning, placement, clock tree synthesis
(CTS), routing and signoff (timing, IR, EM, DRC/LVS)
Coordinate
with block-level PD owners if necessary and ensure seamless
integration at sub-system level.
Analyze
and optimize PPA (Power, Performance, Area) to meet design targets.
Collaborate
with RTL, STA, power DFT and verification for design convergence.
Lead
ECO cycles for timing, congestion and physical signoff closure.
Review
and debug physical verification and timing issues.
Requirements
4-8 years of experience in ASIC/SOC Physical Design.
Strong expertise in industry standard PD tools (Innovus,
Tempus, Voltus, RedHawk, Calibre)
Proven experience in block/sub-system level integration and
signoff flows.
Good understanding of STA, Physical Verification and low-power
design methodologies (UPF/CPF)
Hands on experience with lower process nodes (16nm and below preferred)
Strong debugging and problem solving skills in timing,
congestion and physical verification
Hands on experience in handling Analog custom routes,
understanding specification to meet R and C
Experience in multi-voltage, multi-frequency design
Knowledge of EM/IR-drop analysis and mitigation
Excellent communication and leadership skills