Manager

About the Role :

We are looking for an experienced Manager RTL Design to lead a high-performing ASIC/SoC design team responsible for delivering complex digital IPs and SoC subsystems. The ideal candidate will combine strong technical expertise in RTL design with proven people leadership, project execution, and cross-functional collaboration.

Key Responsibilities :

- Lead and mentor a team of RTL Design Engineers, providing technical guidance and career development.

- Drive RTL design activities from architecture review through RTL implementation, integration, and silicon bring-up.

- Translate product and architectural requirements into scalable micro-architecture and high-quality synthesizable RTL.

- Define project plans, allocate resources, monitor execution, and ensure timely delivery of design milestones.

- Collaborate with Architecture, Verification, DFT, Physical Design, STA, and Validation teams throughout the ASIC development lifecycle.

- Conduct design and code reviews to ensure compliance with coding standards and design methodologies.

- Drive design optimization for performance, power, area (PPA), and quality.

- Support synthesis, timing closure, logic equivalence checking (LEC), and formal verification activities.

- Review functional coverage, verification plans, and design quality metrics.

- Resolve complex design issues and provide technical leadership during silicon bring-up and post-silicon debugging.

- Champion engineering best practices, process improvements, and design automation initiatives.

Required Skills :

- Strong expertise in RTL design using Verilog/SystemVerilog.

- Excellent understanding of digital design fundamentals, computer architecture, and micro-architecture development.

- Strong experience with ASIC/SoC design flows.

- Hands-on experience with AMBA protocols (AXI, AHB, APB).

- Good understanding of synthesis, STA, timing closure, LEC, CDC/RDC, and low-power design techniques.

- Experience with simulation and debugging tools such as VCS, ModelSim, or Xcelium.

- Familiarity with DFT methodologies and SoC integration.

- Strong leadership, stakeholder management, and project execution skills.

Qualifications :

- 10 - 15 years of experience in ASIC/SoC RTL Design.

- Proven experience leading engineering teams and delivering multiple ASIC tape-outs.

Skills

RTL Design, ASIC, SoC, Physical Design, Verification, Verilog, System Verilog, AMBA, Synthesis