ASIC Verification Engineer

Uniconnect • C++ • 1 year ago
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Salary
≈ $48k – $103k per year (Estimated)
Location
In office (Singapore)
Seniority
Staff · 8+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 24, 2026. First seen by Alion on Mar 17, 2025. Uniconnect scores D on the Alion truth index.

Overview
Company
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Uniconnect

Looking for the Top Semiconductor and AI Acquisition Firm in Singapore? UniConnect is your trusted job agency for recruitment solutions in Singapore.
uniconnect.com.sg • Bengaluru • Hyderabad • George Town • Bayan Lepas • Coimbatore • Professional Services • Recruiting & Staffing
  • As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits - developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is simple - to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements

Requirements

  • Experience in UVM verification methodology.
  • Disciplined, quality-minded, and highly driven for excellence.
  • Excellent team player and good communication skills.
  • MSEE/BSEE in Electrical Engineering or Computer Engineering, with 8 years of relevant experience, but are open to fresh graduates with outstanding results.
  • Candidates with relevant experiences would be offered as Senior or Staff, taking on higher responsibilities.
  • Experience in video processing and video analytics is a plus.
  • Passionate and strong in general programming is a plus.

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